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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory32/] [blockMemory/] [implement/] [implement.bat] - Rev 5
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rem Clean up the results directoryrmdir /S /Q resultsmkdir resultsrem Synthesize the VHDL Wrapper Filesecho 'Synthesizing example design with XST';xst -ifn xst.scrcopy blockMemory_exdes.ngc .\results\rem Copy the netlist generated by Coregenecho 'Copying files from the netlist directory to the results directory'copy ..\..\blockMemory.ngc results\rem Copy the constraints files generated by Coregenecho 'Copying files from constraints directory to results directory'copy ..\example_design\blockMemory_exdes.ucf results\cd resultsecho 'Running ngdbuild'ngdbuild -p xc3s500e-fg320-5 blockMemory_exdesecho 'Running map'map blockMemory_exdes -o mapped.ncd -pr iecho 'Running par'par mapped.ncd routed.ncdecho 'Running trce'trce -e 10 routed.ncd mapped.pcf -o routedecho 'Running design through bitgen'bitgen -w routedecho 'Running netgen to create gate level VHDL model'netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
