URL
https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk
Subversion Repositories mod_mult_exp
[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [coregen.cgp] - Rev 5
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET package = fg320
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = false