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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML><HEAD> <TITLE>Analysis & Synthesis Messages</TITLE> <link rel="stylesheet" type="text/css" href="css/reset.css"> <link rel="stylesheet" type="text/css" href="css/base.css"> <link rel="stylesheet" type="text/css" href="css/jquery-ui.css"> <link rel="stylesheet" type="text/css" href="css/jquery.layout-latest.css"> <link rel="stylesheet" type="text/css" href="css/override.css"> <script type="text/javascript" src="js/jquery.min.js"></script> <script type="text/javascript" src="js/jquery-ui.min.js"></script> <script type="text/javascript" src="js/jquery.layout-latest.js"></script> </HEAD> <BODY> <div class="messages"> <ul><li class="info_message">Info: *******************************************************************</li><li class="info_message">Info: Running Quartus II 32-bit Analysis & Synthesis<ul><li class="info_message">Info: Version 12.1 Build 177 11/07/2012 SJ Web Edition</li><li class="info_message">Info: Processing started: Wed Mar 06 16:06:21 2013</li></ul></li><li class="info_message">Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mod_sim_exp -c mod_sim_exp_core</li><li class="warning_message">Warning (20028): Parallel compilation is not licensed and has been disabled</li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram_asym.vhd<ul><li class="info_message">Info (12022): Found design unit 1: operand_ram_asym-Behavioral</li><li class="info_message">Info (12023): Found entity 1: operand_ram_asym</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpramblock_asym.vhd<ul><li class="info_message">Info (12022): Found design unit 1: tdpramblock_asym-structural</li><li class="info_message">Info (12023): Found entity 1: tdpramblock_asym</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpram_asym.vhd<ul><li class="info_message">Info (12022): Found design unit 1: tdpram_asym-behavorial</li><li class="info_message">Info (12023): Found entity 1: tdpram_asym</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram_asym.vhd<ul><li class="info_message">Info (12022): Found design unit 1: modulus_ram_asym-structural</li><li class="info_message">Info (12023): Found entity 1: modulus_ram_asym</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpramblock_asym.vhd<ul><li class="info_message">Info (12022): Found design unit 1: dpramblock_asym-structural</li><li class="info_message">Info (12023): Found entity 1: dpramblock_asym</li></ul></li><li class="warning_message">Warning (10335): Unrecognized synthesis attribute "ram_style" at ../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_asym.vhd(89)</li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_asym.vhd<ul><li class="info_message">Info (12022): Found design unit 1: dpram_asym-behavorial</li><li class="info_message">Info (12023): Found entity 1: dpram_asym</li></ul></li><li class="warning_message">Warning (10335): Unrecognized synthesis attribute "ram_style" at ../SVN/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd(81)</li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/ram/tdpram_generic.vhd<ul><li class="info_message">Info (12022): Found design unit 1: tdpram_generic-behavorial</li><li class="info_message">Info (12023): Found entity 1: tdpram_generic</li></ul></li><li class="warning_message">Warning (10335): Unrecognized synthesis attribute "ram_style" at ../SVN/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd(77)</li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/ram/dpram_generic.vhd<ul><li class="info_message">Info (12022): Found design unit 1: dpram_generic-behavorial</li><li class="info_message">Info (12023): Found entity 1: dpram_generic</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 0 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/std_functions.vhd<ul><li class="info_message">Info (12022): Found design unit 1: std_functions (mod_sim_exp)</li><li class="info_message">Info (12022): Found design unit 2: std_functions-body</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram_gen.vhd<ul><li class="info_message">Info (12022): Found design unit 1: operand_ram_gen-Behavioral</li><li class="info_message">Info (12023): Found entity 1: operand_ram_gen</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram_gen.vhd<ul><li class="info_message">Info (12022): Found design unit 1: modulus_ram_gen-Behavioral</li><li class="info_message">Info (12023): Found entity 1: modulus_ram_gen</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/adder_block.vhd<ul><li class="info_message">Info (12022): Found design unit 1: adder_block-Structural</li><li class="info_message">Info (12023): Found entity 1: adder_block</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd<ul><li class="info_message">Info (12022): Found design unit 1: autorun_cntrl-Behavioral</li><li class="info_message">Info (12023): Found entity 1: autorun_cntrl</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd<ul><li class="info_message">Info (12022): Found design unit 1: cell_1b-Structural</li><li class="info_message">Info (12023): Found entity 1: cell_1b</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd<ul><li class="info_message">Info (12022): Found design unit 1: cell_1b_adder-Behavioral</li><li class="info_message">Info (12023): Found entity 1: cell_1b_adder</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd<ul><li class="info_message">Info (12022): Found design unit 1: cell_1b_mux-Behavioral</li><li class="info_message">Info (12023): Found entity 1: cell_1b_mux</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd<ul><li class="info_message">Info (12022): Found design unit 1: counter_sync-Behavioral</li><li class="info_message">Info (12023): Found entity 1: counter_sync</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd<ul><li class="info_message">Info (12022): Found design unit 1: d_flip_flop-Behavorial</li><li class="info_message">Info (12023): Found entity 1: d_flip_flop</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd<ul><li class="info_message">Info (12022): Found design unit 1: fifo_generic-arch</li><li class="info_message">Info (12023): Found entity 1: fifo_generic</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd<ul><li class="info_message">Info (12022): Found design unit 1: mod_sim_exp_core-Structural</li><li class="info_message">Info (12023): Found entity 1: mod_sim_exp_core</li></ul></li><li class="info_message">Info (12021): Found 1 design units, including 0 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd<ul><li class="info_message">Info (12022): Found design unit 1: mod_sim_exp_pkg (mod_sim_exp)</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd<ul><li class="info_message">Info (12022): Found design unit 1: mont_ctrl-Behavioral</li><li class="info_message">Info (12023): Found entity 1: mont_ctrl</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd<ul><li class="info_message">Info (12022): Found design unit 1: mont_multiplier-Structural</li><li class="info_message">Info (12023): Found entity 1: mont_multiplier</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_dp.vhd<ul><li class="info_message">Info (12022): Found design unit 1: operand_dp-operand_dp_a</li><li class="info_message">Info (12023): Found entity 1: operand_dp</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd<ul><li class="info_message">Info (12022): Found design unit 1: operand_mem-structural</li><li class="info_message">Info (12023): Found entity 1: operand_mem</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd<ul><li class="info_message">Info (12022): Found design unit 1: operand_ram-Behavioral</li><li class="info_message">Info (12023): Found entity 1: operand_ram</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/operands_sp.vhd<ul><li class="info_message">Info (12022): Found design unit 1: operands_sp-operands_sp_a</li><li class="info_message">Info (12023): Found entity 1: operands_sp</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_1b.vhd<ul><li class="info_message">Info (12022): Found design unit 1: register_1b-Behavorial</li><li class="info_message">Info (12023): Found entity 1: register_1b</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_n.vhd<ul><li class="info_message">Info (12022): Found design unit 1: register_n-Behavorial</li><li class="info_message">Info (12023): Found entity 1: register_n</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd<ul><li class="info_message">Info (12022): Found design unit 1: standard_cell_block-Structural</li><li class="info_message">Info (12023): Found entity 1: standard_cell_block</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd<ul><li class="info_message">Info (12022): Found design unit 1: stepping_logic-Behavioral</li><li class="info_message">Info (12023): Found entity 1: stepping_logic</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd<ul><li class="info_message">Info (12022): Found design unit 1: sys_first_cell_logic-Behavorial</li><li class="info_message">Info (12023): Found entity 1: sys_first_cell_logic</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd<ul><li class="info_message">Info (12022): Found design unit 1: sys_last_cell_logic-Behavorial</li><li class="info_message">Info (12023): Found entity 1: sys_last_cell_logic</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd<ul><li class="info_message">Info (12022): Found design unit 1: sys_pipeline-Structural</li><li class="info_message">Info (12023): Found entity 1: sys_pipeline</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd<ul><li class="info_message">Info (12022): Found design unit 1: sys_stage-Structural</li><li class="info_message">Info (12023): Found entity 1: sys_stage</li></ul></li><li class="info_message">Info (12021): Found 2 design units, including 1 entities, in source file /dropbox/svn/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd<ul><li class="info_message">Info (12022): Found design unit 1: x_shift_reg-Behavioral</li><li class="info_message">Info (12023): Found entity 1: x_shift_reg</li></ul></li><li class="info_message">Info (12127): Elaborating entity "fifo_generic" for the top level hierarchy</li><li class="info_message">Info (12128): Elaborating entity "dpram_generic" for hierarchy "dpram_generic:ramblock"</li><li class="info_message">Info (19000): Inferred 1 megafunctions from design logic<ul><li class="info_message">Info (276029): Inferred altsyncram megafunction from the following design logic: "dpram_generic:ramblock|RAM_rtl_0" <ul><li class="info_message">Info (286033): Parameter OPERATION_MODE set to DUAL_PORT</li><li class="info_message">Info (286033): Parameter WIDTH_A set to 32</li><li class="info_message">Info (286033): Parameter WIDTHAD_A set to 6</li><li class="info_message">Info (286033): Parameter NUMWORDS_A set to 33</li><li class="info_message">Info (286033): Parameter WIDTH_B set to 32</li><li class="info_message">Info (286033): Parameter WIDTHAD_B set to 6</li><li class="info_message">Info (286033): Parameter NUMWORDS_B set to 33</li><li class="info_message">Info (286033): Parameter ADDRESS_ACLR_A set to NONE</li><li class="info_message">Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED</li><li class="info_message">Info (286033): Parameter ADDRESS_ACLR_B set to NONE</li><li class="info_message">Info (286033): Parameter OUTDATA_ACLR_B set to NONE</li><li class="info_message">Info (286033): Parameter ADDRESS_REG_B set to CLOCK0</li><li class="info_message">Info (286033): Parameter INDATA_ACLR_A set to NONE</li><li class="info_message">Info (286033): Parameter WRCONTROL_ACLR_A set to NONE</li><li class="info_message">Info (286033): Parameter INIT_FILE set to db/mod_sim_exp.ram0_dpram_generic_6651389b.hdl.mif</li><li class="info_message">Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA</li></ul></li></ul></li><li class="info_message">Info (12130): Elaborated megafunction instantiation "dpram_generic:ramblock|altsyncram:RAM_rtl_0"</li><li class="info_message">Info (12133): Instantiated megafunction "dpram_generic:ramblock|altsyncram:RAM_rtl_0" with the following parameter:<ul><li class="info_message">Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"</li><li class="info_message">Info (12134): Parameter "WIDTH_A" = "32"</li><li class="info_message">Info (12134): Parameter "WIDTHAD_A" = "6"</li><li class="info_message">Info (12134): Parameter "NUMWORDS_A" = "33"</li><li class="info_message">Info (12134): Parameter "WIDTH_B" = "32"</li><li class="info_message">Info (12134): Parameter "WIDTHAD_B" = "6"</li><li class="info_message">Info (12134): Parameter "NUMWORDS_B" = "33"</li><li class="info_message">Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"</li><li class="info_message">Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"</li><li class="info_message">Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"</li><li class="info_message">Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"</li><li class="info_message">Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"</li><li class="info_message">Info (12134): Parameter "INDATA_ACLR_A" = "NONE"</li><li class="info_message">Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"</li><li class="info_message">Info (12134): Parameter "INIT_FILE" = "db/mod_sim_exp.ram0_dpram_generic_6651389b.hdl.mif"</li><li class="info_message">Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"</li></ul></li><li class="info_message">Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_thm1.tdf<ul><li class="info_message">Info (12023): Found entity 1: altsyncram_thm1</li></ul></li><li class="info_message">Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"<ul><li class="info_message">Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL</li></ul></li><li class="info_message">Info (21057): Implemented 140 device resources after synthesis - the final resource count might be different<ul><li class="info_message">Info (21058): Implemented 36 input pins</li><li class="info_message">Info (21059): Implemented 36 output pins</li><li class="info_message">Info (21061): Implemented 36 logic cells</li><li class="info_message">Info (21064): Implemented 32 RAM segments</li></ul></li><li class="info_message">Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings<ul><li class="info_message">Info: Peak virtual memory: 400 megabytes</li><li class="info_message">Info: Processing ended: Wed Mar 06 16:06:24 2013</li><li class="info_message">Info: Elapsed time: 00:00:03</li><li class="info_message">Info: Total CPU time (on all processors): 00:00:03</li></ul></li></ul></div> <noscript>JavaScript must be enabled to view the report.</noscript> </BODY> </HTML>
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