Subversion Repositories modular_oscilloscope

-------------------------------------------------------------------------------------------------100
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: channel_selector.vhd
--| Version: 0.2
--| Tested in: Actel A3PE1500
--|   Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   CONTROL - Channel Selector
--|   This controls the comunication with the daq module. 
--|   
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.1   | jul-2009 | First testing
--|   0.2   | jul-2009 | Added generic number of channel
----------------------------------------------------------------------------------------------------
--| Copyright © 2009, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
--==================================================================================================
-- TODO
-- · Speed up the design
--==================================================================================================
 
 
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
 
 
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
entity channel_selector is
  generic(
    N_CHANNELS: integer := 16 -- number of channels 
  );
  port(
    channels_I:         in  std_logic_vector(N_CHANNELS-1 downto 0);
    channel_number_O:   out std_logic_vector(3 downto 0);
    clk_I:              in  std_logic;
    enable_I:           in  std_logic;
    reset_I:            in  std_logic                                                        
  );
end entity channel_selector;
 
 
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
architecture ARCH01 of channel_selector is
  constant CHANNEL_WIDTH: integer := integer(ceil(log2(real(N_CHANNELS))));
 
  signal channel:       unsigned(CHANNEL_WIDTH-1 downto 0);
  signal next_channel:  unsigned(CHANNEL_WIDTH-1 downto 0);
 
 
begin 
 
  --------------------------------------------------------------------------------------------------
  -- Output
  channel_number_O <= (3 downto CHANNEL_WIDTH => '0') & std_logic_vector(channel);
  --channel_number_O <=  std_logic_vector(channel);
  --------------------------------------------------------------------------------------------------
  -- Combinational selection
 
  P_comb: process(channel,channels_I) 
    variable j :    integer range 0 to N_CHANNELS-1;
    variable index: integer range 0 to N_CHANNELS-1;
  begin
 
 
  --    -- for i in 0 to N_CHANNELS loop
  --       if i = to_integer(channel) then
  --         exit;
  --       end if;
  --      end loop;
 
  --  for i in 0 to N_CHANNELS loop
      --i := to_natural(channel);
      for j in 0 to N_CHANNELS-1 loop
 
        if (j + to_integer(channel) + 1) > (N_CHANNELS - 1) then
          index := j + to_integer(channel) + 1 - N_CHANNELS;
        else
          index := j + to_integer(channel) + 1;
        end if;
 
        if channels_I(index) = '1' then           
          next_channel <= to_unsigned(index, CHANNEL_WIDTH);
          exit;
        else
          next_channel <= channel;
        end if;
 
      end loop;
 
 
 
 
 
 
 
--     for i in 0 to N_CHANNELS loop
--       if channel = to_unsigned(i, 4) then           
--         for j in i+1 to (2*N_CHANNELS)-1 loop
--           if j > N_CHANNELS-1 then
--             index := j - N_CHANNELS;
--           else
--             index := j;
--           end if;
--         
--           if channels_I(index) = '1' then
--             next_channel <= to_unsigned(index, CHANNEL_WIDTH);
--             exit;
--           else
--             next_channel <= channel;
--           end if;
--         end loop;
--         exit;
--       else
--         next_channel <= channel;
--       end if;
--     end loop;  
 
  end process; 
 
 
  --------------------------------------------------------------------------------------------------
  -- Clocked
 
  P_clock: process(enable_I, reset_I, next_channel, clk_I) 
  begin
    if clk_I'event and clk_I = '1' then
      if reset_I = '1' then
        channel <= (others => '0');
      elsif enable_I = '1' then
        channel <= next_channel;
      end if;
    end if;
  end process; 
 
 
 
 
end architecture;