Subversion Repositories modular_oscilloscope

----------------------------------------------------------------------------------------------------
--| Modular Oscilloscope
--| UNSL - Argentina
--|
--| File: adq.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   Adquisition control module. 
--|   It drives the ADC chips.
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.01   | apr-2008 | First testing
--|   0.10   | apr-2009 | First release
----------------------------------------------------------------------------------------------------
--| Copyright ® 2009, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
 
--| Wishbone Rev. B.3 compatible
----------------------------------------------------------------------------------------------------
 
 
--| TODO:
--|  Access to both channels in consecutive reads  
 
 
 
-- Esta primera versión está realizada específicamente para controlar el ADC AD9201. Otras
-- versiones podrán ser más genéricas.
 
 
-- ADR    configuración (señal config)
-- ADR+1  datos canal 1
-- ADR+2  datos canal 2
-- ADR+3  sin usar
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.NUMERIC_STD.ALL;
--use work.adq_pgk.all;
 
entity adq is
  generic (
    DEFALT_CONFIG : std_logic_vector := "0000100000000000"
                                      -- bits 8 a 0       clk_pre_scaler
                                      -- bits 9           clk_pre_scaler_ena
                                      -- bit 10           adc_sleep
                                      -- bit 11           adc_chip_sel
                                      -- bits 12 a 15     sin usar
 
                                      -- si clk_pre_scaler_ena = 1
                                      -- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2)
                                      -- sino frecuencia_adc = frecuencia_wbn
  );
  port(
    -- Externo
    adc_data:     in    std_logic_vector (9 downto 0);
    adc_sel:      out   std_logic;
    adc_clk:      out   std_logic;
    adc_sleep:    out   std_logic;
    adc_chip_sel: out   std_logic;
 
 
    --  Interno
    RST_I:  in  std_logic;  
    CLK_I:  in  std_logic;  
    DAT_I:  in  std_logic_vector (15 downto 0);
    ADR_I:  in  std_logic_vector (1 downto 0);
    CYC_I:  in  std_logic;  
    STB_I:  in  std_logic; 
    WE_I:   in  std_logic;
    DAT_O:  out std_logic_vector (15 downto 0);
    ACK_O:  out std_logic 
  );
end adq;
 
 
architecture beh1 of adq is
  -- Tipos
  type data_array is array(0 to 2) of std_logic_vector(15 downto 0);
 
 
                --   type arr is array(0 to 3) of std_logic_vector(15 downto 0);
                -- 
                -- signal arr_a : arr;
                -- signal vec_0, vec_1, vec_2, vec_3 : std_logic vector(15 downto 0);
                -- ....
                -- arr_a(0) <= vec_0;
                -- arr_a(1) <= vec_1;
                -- ....
 
  -- Registros de configuración
  signal config:   std_logic_vector (15 downto 0);
  signal selector: data_array;
 
  -- Registros
  signal count: std_logic_vector (9 downto 0);
 
  -- Señales 
  signal s_adc_clk, s_adc_sleep, s_adc_chip_sel: std_logic; 
  signal data_ack_ready:      std_logic; -- habilita confirmación de datos
  signal conf_ack_ready:      std_logic; -- habilita confirmación de escritura de configuración
  signal clk_pre_scaler:      std_logic_vector (8 downto 0);
  signal clk_pre_scaler_ena:  std_logic;
  --signal clk_enable: std_logic_vector (9 downto 0);
 
begin
  --------------------------------------------------------------------------------------------------
  -- Asignaciones
  ---- Comunicación interna (Wishbone)
  selector(0) <= config;
  selector(1) <= (config'length - 1 downto adc_data'length => '0' ) & adc_data;
  selector(2) <= (config'length - 1 downto adc_data'length => '0' ) & adc_data;
  --selector(3) <= (others => '0' ); -- Sin usar
 
  ---- Registro de configuración config
  clk_pre_scaler <= config(8 downto 0);
  clk_pre_scaler_ena <= config(9); 
  s_adc_sleep <= config(10);
  s_adc_chip_sel <= config(11);
  -- sin asignar <= config(13); para usar en otras implementaciones
  -- sin asignar <= config(14);
  -- sin asignar <= config(15);
 
  ---- Comunicación externa (AD)
  adc_sleep <= s_adc_sleep;
  adc_chip_sel <= s_adc_chip_sel;
 
 
 
  --------------------------------------------------------------------------------------------------
  -- Generación de adc_clk
  process (CLK_I, clk_pre_scaler,RST_I,count, clk_pre_scaler_ena) 
  begin
    if RST_I = '1' then
      count <= (others => '0');
      s_adc_clk <= '0';
    elsif clk_pre_scaler_ena = '1' then
      if CLK_I'event and CLK_I = '1' then
        count <= count + 1;
        if count = clk_pre_scaler  then
          s_adc_clk <= not(s_adc_clk);
          count <= (others => '0');
        end if;        
      end if;
    else  
      count <= (others => '0');
      s_adc_clk <= CLK_I;
    end if;
  end process;
  adc_clk <= s_adc_clk;
 
  --------------------------------------------------------------------------------------------------
  -- Generación ack
  ACK_O <= CYC_I and STB_I and (data_ack_ready or conf_ack_ready);
  data_ack_ready  <=  '1' when (unsigned(count) = 0 and WE_I = '0' and unsigned(ADR_I) /= 0 and s_adc_clk = '1') 
                      or (clk_pre_scaler_ena /= '1') 
                  else
                      '0';                    
    -- count = 0 asegura que el dato actual ya fue leído
 
  conf_ack_ready  <=  '1' when unsigned(ADR_I) = 0  else
                      '0';
 
  --------------------------------------------------------------------------------------------------
  -- Selección de canal
  adc_sel <=  '1' when unsigned(ADR_I) = 2 else   -- selecciona canal Q
              '0';                                -- selecciona canal I
 
 
  --------------------------------------------------------------------------------------------------
  -- Lectura y escritura de datos
  ---- Generación de DAT_O
  DAT_O   <=  selector(conv_integer(ADR_I));
 
  ---- Almacenado de registro de configuración
  process (CLK_I, ADR_I, RST_I, DAT_I) 
  begin
 
    if CLK_I'event and CLK_I = '1' then
      if RST_I = '1' then
        config <= DEFALT_CONFIG;
      elsif WE_I = '1' and  CYC_I = '1' and STB_I = '1' then
        if unsigned(ADR_I) = 0 then
          config <= DAT_I; 
        end if;
      end if;             
    end if;
 
  end process;
 
 
end architecture beh1;