Subversion Repositories modular_oscilloscope

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--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: modullar_oscilloscope_tbench_text.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--|   Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   This file is only for test purposes. 
--|
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.1   | aug-2009 | First release
----------------------------------------------------------------------------------------------------
--| Copyright © 2009, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
--==================================================================================================
-- TO DO
-- · Full full test
--==================================================================================================
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
 
 
 
entity ctrl_tb_simple_clock is
  port ( 
    CLK_PERIOD: in time;-- := 20 ns;
    CLK_DUTY:  in  real; -- := 0.5;
    active:  in     boolean;
    clk_o:   out    std_logic
  );
end entity ctrl_tb_simple_clock ;
 
architecture beh of ctrl_tb_simple_clock is
begin
  P_main: process
  begin
    wait until active;
    while (active = true) loop
      clk_o <= '0';
      wait for CLK_PERIOD * (100.0 - clk_Duty)/100.0;
      clk_o <= '1';
      wait for CLK_PERIOD * clk_Duty/100.0;
    end loop;                   
    clk_o <= '0';
    wait;      
  end process;
end architecture beh;
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
 
 
-- Additional libraries used by Model Under Test.
use work.ctrl_pkg.all;
use work.daq_pkg.all;
use work.memory_pkg.all;
use work.eppwbn_pkg.all;
 
entity stimulus is
  port(
 -- ADC
    adc_data_I:     inout    std_logic_vector (9 downto 0) := 0;
    adc_sel_O:      in   std_logic;
    adc_clk_O:      in   std_logic;
    adc_sleep_O:    in   std_logic;
    adc_chip_sel_O: in   std_logic;
 
    -- EPP
    nStrobe_I:      inout std_logic;                       --  HostClk/nWrite 
    Data_IO:        inout std_logic_vector (7 downto 0);--   AD8..1 (Data1..Data8)
    nAck_O:         in std_logic;                      --  PtrClk/PeriphClk/Intr
    busy_O:         in std_logic;                      --  PtrBusy/PeriphAck/nWait
    PError_O:       in std_logic;                      --  AckData/nAckReverse
    Sel_O:          in std_logic;                      --  XFlag (Select)
    nAutoFd_I:      inout std_logic;                       --  HostBusy/HostAck/nDStrb
    PeriphLogicH_O: in std_logic;                      --  (Periph Logic High)
    nInit_I:        inout std_logic;                       --  nReverseRequest
    nFault_O:       in std_logic;                      --  nDataAvail/nPeriphRequest
    nSelectIn_I:    inout std_logic;                       --  1284 Active/nAStrb
 
    -- Peripherals
    reset_I:    inout std_logic; 
    pll_clk_I:  inout std_logic  -- clock signal go to pll, and is divided in two clocks
  );
 
end stimulus;
 
architecture STIMULATOR of stimulus is
 
  -- Control Signal Declarations
  signal tb_InitFlag : boolean := false;
  signal tb_ParameterInitFlag : boolean := false;
  signal i: std_logic;
 
  -- Parm Declarations
  signal clk_Duty :   real := 0.0;
  signal clk_Period : time := 0 ns;
 
begin
  --------------------------------------------------------------------------------------------------
  -- Parm Assignment Block
  P_AssignParms : process
    variable clk_Duty_real :    real;
    variable clk_Period_real :  real;
  begin
    -- Basic parameters
    clk_Period_real := 20.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
    clk_Period <= clk_Period_real * 1 ns;
    clk_Duty_real := 50.0;
    clk_Duty <= clk_Duty_real;
 
    tb_ParameterInitFlag <= true;
 
    wait;
  end process;
 
 
  --------------------------------------------------------------------------------------------------
  -- Clocks
  -- Clock Instantiation
  tb_clk: entity work.tb_simple_clock 
  port map ( 
    clk_Period => clk_Period,
    clk_Duty => clk_Duty,
    active => tb_InitFlag,
    clk_o => pll_clk_I
  );
 
 
  --------------------------------------------------------------------------------------------------
  -- Clocked Sequences
  P_virtual_adc: process (adc_clk_O)
    variable data1: std_logic_vector(9 downto 0) := 1; -- odd
    variable data2: std_logic_vector(9 downto 0) := 0; -- pair
  begin
    if adc_clk_O'event and adc_clk_O = '1' then
      data1 <= data1 + 2;
      data2 <= data2 + 2;
    end if;  
 
 
    case adc_sel_O is
      when '0' => 
         adc_data_I <= data1;
      when others => 
         adc_data_I <= data2;   
    end case;
  end process;
 
 
  --------------------------------------------------------------------------------------------------
  -- Sequence: Unclocked
  P_Unclocked : process
 
  begin
    wait until tb_ParameterInitFlag;
    tb_InitFlag <= true;
 
    load_I <= '0';
    RST_I <= '1';
    STB_I_port <= '1';
    CYC_I_port <= '1';
    WE_I_port <= '0';
    initial_address_I <= B"01_0000_0000_0000";
    biggest_address_I <= B"11_1100_0000_0000";
    pause_address_I   <= B"00_0000_1000_0000";
    enable_I <= '1';
      wait for 1.5 * clk_Period;
 
    RST_I <= '0';
      wait for 1.0 * clk_Period;
 
    load_I <= '1';    
      wait for 1.0 * clk_Period;
 
 
 
 
    load_I <= '0';    
    wait until ADR_O_mem = B"00_0000_1000_0000";
      wait for 8.0 * clk_Period;
 
    pause_address_I   <= B"01_0000_0000_0000";
      wait for 20.0 * clk_Period;
 
    enable_I <= '0';
      wait for 8.0 * clk_Period;
 
    enable_I <= '1';
 
 
    wait until finish_O = '1';
      wait for 2.0 * clk_Period;
 
    tb_InitFlag <= false;
    wait;
 
 
  end process;
 
 
 
  --------------------------------------------------------------------------------------------------
  -- Conditional signals
 
  P_mem: process(STB_O_mem, DAT_I_mem, CYC_O_mem, CLK_I, RST_I,i)
 
  begin
    if STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
      ACK_I_mem <= '1';
    else
      ACK_I_mem <= '0';
    end if;
 
    if CLK_I'event and CLK_I = '1' then 
      if RST_I = '1' then 
        DAT_I_mem <= (others => '0');
      elsif STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then 
        DAT_I_mem <= DAT_I_mem + 1;
      end if;
    end if;
 
    if CLK_I'event and CLK_I = '1' then 
      if RST_I = '1' then 
        i <= '0';
      elsif STB_O_mem = '1' and CYC_O_mem = '1' then 
        i <= not(i);
      end if;
    end if;
 
  end process;
 
 
 
end architecture STIMULATOR;
 
 
 
 
 
 
 
 
 
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
 library ieee, std;
 use ieee.std_logic_1164.all;
 
 
 
-- Additional libraries used by Model Under Test.
-- ...
 
entity testbench is
  generic (
    MEM_ADD_WIDTH:  integer := 14
  );
end testbench;
 
architecture tbGeneratedCode of testbench is
    -- ADC
    signal adc_data_I:      std_logic_vector (9 downto 0);
    signal adc_sel_O:       std_logic;
    signal adc_clk_O:       std_logic;
    signal adc_sleep_O:     std_logic;
    signal adc_chip_sel_O:  std_logic;
    -- EPP
    signal nStrobe_I:       std_logic;
    signal Data_IO:         std_logic_vector (7 downto 0);  
    signal nAck_O:          std_logic;
    signal busy_O:          std_logic;
    signal PError_O:        std_logic;
    signal Sel_O:           std_logic;
    signal nAutoFd_I:       std_logic;
    signal PeriphLogicH_O:  std_logic;
    signal nInit_I:         std_logic;
    signal nFault_O:        std_logic;
    signal nSelectIn_I:     std_logic;
    -- Peripherals
    signal reset_I:     std_logic; 
    signal pll_clk_I:   std_logic;
begin
  --------------------------------------------------------------------------------------------------
  -- Instantiation of Stimulus.
  U_stimulus_0 : entity work.stimulus
    generic map (
    MEM_ADD_WIDTH=> MEM_ADD_WIDTH
    )
    port map (
      -- ADC
      adc_data_I => adc_data_I,
      adc_sel_O => adc_sel_O,
      adc_clk_O => adc_clk_O,
      adc_sleep_O => adc_sleep_O,
      adc_chip_sel_O => adc_chip_sel_O,
      -- EPP
      nStrobe_I => nStrobe_I,
      Data_IO => Data_IO,
      nAck_O => nAck_O,
      busy_O => busy_O,
      PError_O => PError_O,
      Sel_O => Sel_O,
      nAutoFd_I => nAutoFd_I,
      PeriphLogicH_O =>PeriphLogicH_O ,
      nInit_I => nInit_I,
      nFault_O => nFault_O,
      nSelectIn_I => nSelectIn_I,
      -- Peripherals
      reset_I => reset_I,
      pll_clk_I => pll_clk_I
    );
 
  --------------------------------------------------------------------------------------------------
  -- Instantiation of Model Under Test.
  U_outman_0 : entity work.modular_oscilloscope --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
    generic map (
      MEM_ADD_WIDTH=> MEM_ADD_WIDTH
    )
    port map (
      -- ADC
      adc_data_I => adc_data_I,
      adc_sel_O => adc_sel_O,
      adc_clk_O => adc_clk_O,
      adc_sleep_O => adc_sleep_O,
      adc_chip_sel_O => adc_chip_sel_O,
      -- EPP
      nStrobe_I => nStrobe_I,
      Data_IO => Data_IO,
      nAck_O => nAck_O,
      busy_O => busy_O,
      PError_O => PError_O,
      Sel_O => Sel_O,
      nAutoFd_I => nAutoFd_I,
      PeriphLogicH_O =>PeriphLogicH_O ,
      nInit_I => nInit_I,
      nFault_O => nFault_O,
      nSelectIn_I => nSelectIn_I,
      -- Peripherals
      reset_I => reset_I,
      pll_clk_I => pll_clk_I
    );
 
end tbGeneratedCode;
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