OpenCores
URL https://opencores.org/ocsvn/motion_estimation_processor/motion_estimation_processor/trunk

Subversion Repositories motion_estimation_processor

[/] [motion_estimation_processor/] [trunk/] [netlist/] [reference_macroblock_memory64.edn] - Rev 2

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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2008 1 11 15 6 58)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_sinit_value = 0 ")
       (comment "c_has_en = 0 ")
       (comment "c_reg_inputs = 0 ")
       (comment "c_yclk_is_rising = 1 ")
       (comment "c_ysinit_is_high = 1 ")
       (comment "c_ywe_is_high = 1 ")
       (comment "c_yprimitive_type = 16kx1 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_has_rdy = 0 ")
       (comment "c_write_mode = 0 ")
       (comment "c_width = 64 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_nd = 0 ")
       (comment "c_has_we = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_has_rfd = 0 ")
       (comment "c_has_din = 1 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_yen_is_high = 1 ")
       (comment "c_family = spartan3 ")
       (comment "InstanceName = reference_macroblock_memory64 ")
       (comment "c_depth = 800 ")
       (comment "c_has_default_data = 1 ")
       (comment "c_limit_data_pitch = 18 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_yydisable_warnings = 1 ")
       (comment "c_mem_init_file = mif_file_16_1 ")
       (comment "c_default_data = 0 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_addr_width = 10 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell RAMB16_S18 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WE (direction INPUT))
                   (port EN (direction INPUT))
                   (port SSR (direction INPUT))
                   (port CLK (direction INPUT))
                   (port (rename DI_0_ "DI<0>") (direction INPUT))
                   (port (rename DI_1_ "DI<1>") (direction INPUT))
                   (port (rename DI_2_ "DI<2>") (direction INPUT))
                   (port (rename DI_3_ "DI<3>") (direction INPUT))
                   (port (rename DI_4_ "DI<4>") (direction INPUT))
                   (port (rename DI_5_ "DI<5>") (direction INPUT))
                   (port (rename DI_6_ "DI<6>") (direction INPUT))
                   (port (rename DI_7_ "DI<7>") (direction INPUT))
                   (port (rename DI_8_ "DI<8>") (direction INPUT))
                   (port (rename DI_9_ "DI<9>") (direction INPUT))
                   (port (rename DI_10_ "DI<10>") (direction INPUT))
                   (port (rename DI_11_ "DI<11>") (direction INPUT))
                   (port (rename DI_12_ "DI<12>") (direction INPUT))
                   (port (rename DI_13_ "DI<13>") (direction INPUT))
                   (port (rename DI_14_ "DI<14>") (direction INPUT))
                   (port (rename DI_15_ "DI<15>") (direction INPUT))
                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))
                   (port (rename DO_1_ "DO<1>") (direction OUTPUT))
                   (port (rename DO_2_ "DO<2>") (direction OUTPUT))
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                   (port (rename DO_7_ "DO<7>") (direction OUTPUT))
                   (port (rename DO_8_ "DO<8>") (direction OUTPUT))
                   (port (rename DO_9_ "DO<9>") (direction OUTPUT))
                   (port (rename DO_10_ "DO<10>") (direction OUTPUT))
                   (port (rename DO_11_ "DO<11>") (direction OUTPUT))
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                   (port (rename DO_13_ "DO<13>") (direction OUTPUT))
                   (port (rename DO_14_ "DO<14>") (direction OUTPUT))
                   (port (rename DO_15_ "DO<15>") (direction OUTPUT))
                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))
                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))
                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))
                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))
                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))
                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))
                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))
                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))
                   (port (rename ADDR_8_ "ADDR<8>") (direction INPUT))
                   (port (rename ADDR_9_ "ADDR<9>") (direction INPUT))
                   (port (rename DIP_0_ "DIP<0>") (direction INPUT))
                   (port (rename DIP_1_ "DIP<1>") (direction INPUT))
                   (port (rename DOP_0_ "DOP<0>") (direction OUTPUT))
                   (port (rename DOP_1_ "DOP<1>") (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell reference_macroblock_memory64
 (cellType GENERIC) (view view_1 (viewType NETLIST)
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   (port ( rename clk "clk") (direction INPUT))
   (port ( array ( rename din "din<63:0>") 64 ) (direction INPUT))
   (port ( rename we "we") (direction INPUT))
   (port ( array ( rename dout "dout<63:0>") 64 ) (direction OUTPUT))
   )
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    (joined
      (portRef (member dout 63))
      (portRef DO_0_ (instanceRef B6))
    )
   )
   (net (rename N146 "we")
    (joined
      (portRef we)
      (portRef WE (instanceRef B6))
      (portRef WE (instanceRef B10))
      (portRef WE (instanceRef B14))
      (portRef WE (instanceRef B18))
    )
   )
))))
(design reference_macroblock_memory64 (cellRef reference_macroblock_memory64 (libraryRef test_lib))
  (property X_CORE_INFO (string "blkmemsp_v6_1, Coregen 8.2.03i"))
  (property PART (string "xc3s1500-fg456-5") (owner "Xilinx")))
)

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