Subversion Repositories motion_estimation_processor

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file D:\projects\me_interpolation_16m\open_source_core\syn\me_top.prj
#-- Written on Wed Aug 26 12:22:58 2009


#add_file options
add_file -vhdl -lib work "../src_me/config.vhd"
add_file -vhdl -lib work "../src_me/forward_engine.vhd"
add_file -vhdl -lib work "../src_me/concatenate64.vhd"
add_file -vhdl -lib work "../src_me/current_macroblock_memory64.vhd"
add_file -vhdl -lib work "../src_me/distance_engine64.vhd"
add_file -vhdl -lib work "../src_me/dual_port_component.vhd"
add_file -vhdl -lib work "../src_me/range_checker.vhd"
add_file -vhdl -lib work "../src_me/me_control_unit.vhd"
add_file -vhdl -lib work "../src_me/me_engine.vhd"
add_file -vhdl -lib work "../src_me/phy_address.vhd"
add_file -vhdl -lib work "../src_me/point_memory.vhd"
add_file -vhdl -lib work "../src_me/program_memory.vhd"
add_file -vhdl -lib work "../src_me/sad_selector.vhd"
add_file -vhdl -lib work "../src_me/reg_memory_dp.vhd"
add_file -vhdl -lib work "../src_me/register_file.vhd"
add_file -vhdl -lib work "../src_me/reference_memory64_remap.vhd"
add_file -vhdl -lib work "../src_me/reference_macroblock_memory64.vhd"
add_file -vhdl -lib work "../src_me/reference_memory64_dp_large.vhd"
add_file -vhdl -lib work "../src_me/me_top.vhd"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology SPARTAN3
set_option -part XC3S1500
set_option -package FG320
set_option -speed_grade -4

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency 200.000
set_option -run_prop_extract 0
set_option -fanout_limit 10000
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -fixgatedclocks 0
set_option -retiming 0
set_option -modular 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/me_top.edf"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "rev_1"