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For more info see http://www.lyx.org/\lyxformat 508\begin_document\begin_header\save_transient_properties true\origin unavailable\textclass scrreprt\begin_preamble\usepackage[pdftitle={MPEG-2 Decoder User's Guide},pdfauthor={Koenraad De Vleeschauwer},bookmarks]{hyperref}\sloppy\usepackage{microtype}\renewcommand{\headrulewidth}{0.4pt} \renewcommand{\footrulewidth}{0.4pt}\renewcommand{\chaptermark}[1]{%\markboth{\thechapter.\ #1}{}}\rhead{\sffamily \nouppercase{\leftmark}}\fancyhead[LE,RO]{\sffamily \leftmark}\fancyhead[LO,RE]{\sffamily kdv electronics}\fancyhead[C]{}\fancyfoot[LO,RE]{\sffamily MPEG2 Decoder User Guide}\fancyfoot[LE,RO]{\sffamily \thepage}\fancyfoot[C]{\sffamily \today}\fancypagestyle{plain}{%\fancyhead[LE,RO]{}\fancyhead[LO,RE]{}\fancyhead[C]{}\renewcommand{\headrulewidth}{0pt}\renewcommand{\footrulewidth}{0.4pt}}\end_preamble\use_default_options false\maintain_unincluded_children false\language english\language_package default\inputencoding auto\fontencoding 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default\quotes_language english\papercolumns 1\papersides 2\paperpagestyle fancy\tracking_changes false\output_changes false\html_math_output 0\html_css_as_file 0\html_be_strict false\end_header\begin_body\begin_layout TitleMPEG-2 Decoder User Guide\end_layout\begin_layout AuthorKoenraad De Vleeschauwer\begin_inset Newline newline\end_inset\family typewriterkdv@kdvelectronics.eu\end_layout\begin_layout Section*\begin_inset ERTstatus open\begin_layout Plain Layout\backslashthispagestyle{empty}\end_layout\end_insetCopyright Notice\end_layout\begin_layout StandardCopyright\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcopyright\end_layout\end_inset2007-2009, Koenraad De Vleeschauwer.\end_layout\begin_layout StandardRedistribution and use in source (\SpecialChar LyXformat) and `compiled' forms (PDF, PostScript, HTML, RTF, etc.), with or without modification, are permitted providedthat the following conditions are met:\end_layout\begin_layout EnumerateRedistributions of source code (\SpecialChar LyXformat) must retain the above copyrightnotice, this list of conditions and the following disclaimer.\end_layout\begin_layout EnumerateRedistributions in compiled form (transformed to other DTDs, converted toPDF, PostScript, HTML, RTF, and other formats) must reproduce the abovecopyright notice, this list of conditions and the following disclaimerin the documentation and/or other materials provided with the distribution.\end_layout\begin_layout EnumerateThe name of the author may not be used to endorse or promote products derivedfrom this documentation without specific prior written permission.\end_layout\begin_layout Standard\noun onThis documentation is provided by the author\begin_inset Quotes eld\end_insetas is" and any express or implied warranties, including, but not limitedto, the implied warranties of merchantability and fitness for a particularpurpose are disclaimed.In no event shall the author be liable for any direct, indirect, incidental,special, exemplary, or consequential damages (including, but not limitedto, procurement of substitute goods or services; loss of use, data, orprofits; or business interruption) however caused and on any theory ofliability, whether in contract, strict liability, or tort (including negligenceor otherwise) arising in any way out of the use of this documentation,even if advised of the possibility of such damage.\end_layout\begin_layout Section*MPEG-2 License Notice\end_layout\begin_layout StandardCommercial implementations of MPEG-1 and MPEG-2 video, including shareware,are subject to royalty fees to patent holders.Many of these patents are general enough such that they are unavoidableregardless of implementation design.\end_layout\begin_layout Standard\noun onMPEG-2 intermediate product.Use of this product in any manner that complies with the MPEG-2 standardis expressly prohibited without a license under applicable patents in theMPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C.,250 Stelle Street, suite 300, Denver, Colorado 80206.\end_layout\begin_layout Standard\begin_inset CommandInset tocLatexCommand tableofcontents\end_inset\end_layout\begin_layout Chapter\begin_inset CommandInset labelLatexCommand labelname "cha:Processor-Interface"\end_insetProcessor Interface\end_layout\begin_layout StandardAn MPEG2 decoder, implemented in Verilog, is presented.Chapter\begin_inset CommandInset refLatexCommand refreference "cha:Processor-Interface"\end_insetdescribes the decoder for the software engineer who wishes to write a devicedriver.\end_layout\begin_layout SectionDecoder Block Diagram\end_layout\begin_layout Standard\align center\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Graphicsfilename blockdiagram.psheight 96page%keepAspectRatioclip\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:Decoder-Block-Diagram"\end_insetDecoder Block Diagram\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout StandardFigure\begin_inset CommandInset refLatexCommand refreference "fig:Decoder-Block-Diagram"\end_insetshows the MPEG2 decoder block diagram.An external source such as a DVB tuner or DVD drive provides an MPEG2 stream.The video elementary stream is extracted and sent to the decoder.The\emph onvideo buffer\emph defaultacts as a fifo between the incoming MPEG2 video stream and the variablelength decoder.The video buffer evens out temporary differences between the bitrate ofthe incoming MPEG2 bitstream and the bitrate at which the decoder parsesthe bitstream.\end_layout\begin_layout StandardThe MPEG2 codec is a variable length codec; codewords which occur oftenoccupy less bits than codewords which occur only rarely.\emph onGetbits\emph defaultprovides a sliding window over the incoming stream.As the codewords have a variable length, the sliding window moves forwarda variable amount of bits at a time.\end_layout\begin_layout Standard\emph onVariable length decoding\emph defaultdoes the actual parsing of the bitstream.Variable length decoding stores stream parameters such as horizontal andvertical resolution, and produces run/length values and motion vectors.Run/length values and motion vectors are different ways of describing animage.The run/length values describe an image as compressed data contained withinthe bitstream.The motion vectors describe an image as a mosaic of already decoded images.\end_layout\begin_layout Standard\emph onRun-length decoding, inverse quantizing\emph defaultand\emph oninverse discrete cosine transform\emph defaultdecompress the run/length values.\end_layout\begin_layout Standard\emph onMotion compensation\emph defaultretrieves already decoded images from memory and applies the motion vectortranslations.\end_layout\begin_layout StandardThe reconstructed image is the sum of the decompressed run/length valuesand translated pieces of already decoded images.The reconstructed image is stored in the\shape italicframe store\shape defaultfor later display and reference.\end_layout\begin_layout StandardThe frame store receives requests to store and retrieve pixels from threedifferent sources:\end_layout\begin_layout Itemize\emph onmotion compensation\emph default, which writes reconstructed image frames to memory\end_layout\begin_layout Itemize\emph onchroma resampling\emph default, which reads reconstructed image frames from memory for displaying\end_layout\begin_layout Itemizewrites to the\emph onon-screen display\emph default, under software control.\end_layout\begin_layout StandardSome of these blocks have multiple accesses to the frame store.Within the MPEG2 decoder a total of six memory read or write requests mayoccur simultaneously.The frame store prioritizes these requests and serializes them into a singlestream of memory read/write requests, which is sent to the memory controller.\end_layout\begin_layout StandardThe\emph onmemory controller\emph defaultis external to the MPEG2 decoder.The memory controller handles the low-level details of interfacing withthe memory chips.If memory is static RAM, interfacing requires little more than a buffer;dynamic memory requires a more complex controller.\end_layout\begin_layout StandardThe MPEG2 decoder accepts 4:2:0 format video, in which color and brightnessinformation have a different resolution: color information (chrominance)is sent at half the horizontal and half the vertical resolution of brightnessinformation (luminance).This makes sense because the human eye uses different mechanisms to perceivecolor and brightness; and the different mechanisms used have differentsensitivities.\end_layout\begin_layout StandardSending color information at half the horizontal and half the vertical resolution of brightness information implies the reconstructed image in the framestore has only one color pixel for every four brightness pixels.Assigning the same color information to the four pixels of brightness information would result in a chunky image.\emph onChroma resampling\emph defaultdoes horizontal and vertical interpolation of the color information, resultingin a smooth color image.\end_layout\begin_layout StandardA\emph ondot clock\emph defaultmarks the frequency at which pixels are sent to the display.The dot clock is external to the MPEG2 decoder and can be either free runningor synchronized to another clock.\end_layout\begin_layout StandardThe\emph onvideo synchronization generator\emph defaultcounts pixels, lines and image frames at the dot clock frequency.At any given moment, the video synchronization generator knows the horizontaland vertical coordinate of the pixel to be displayed.\end_layout\begin_layout StandardThe pixels generated in chroma resampling and the coordinates generatedby the video synchronization generator are joined in the\emph onmixer\emph default.The result is a stream of pixels, at the current horizontal/vertical coordinate, at the dot clock frequency.\end_layout\begin_layout StandardAt this point the\emph onon-screen display\emph defaultis added.The on-screen display has the same resolution as the video and uses a 256-colorpalette.Software can choose to put the on-screen display on top, completely hidingthe video; or to blend on-screen display and video, as if they were twotranslucent glass plates.\end_layout\begin_layout StandardThe MPEG2 decoder works with chrominance (color) and luminance (brightness)information throughout.The final step is converting chrominance and luminance to red, green andblue in\emph onyuv2rgb\emph default.The red, green and blue information is the output of the decoder.\end_layout\begin_layout SectionPorts\end_layout\begin_layout StandardTable\begin_inset CommandInset refLatexCommand refreference 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Text\begin_layout Plain Layout-\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Ports"\end_insetPorts\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout SubsectionClocks\end_layout\begin_layout StandardUp to three different clocks may be supplied to the MPEG2 decoder.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterclk\family defaultMain decoder clock, input.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterdot_clk\family defaultVideo clock, input.Variable frequency, varying with current video modeline.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_clk\family defaultMemory Controller Clock, input.\end_layout\begin_layout StandardThe decoder produces pixels at a maximum rate of one per\family typewriterclk\family defaultcycle.\end_layout\begin_layout SubsectionReset\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterrst\family defaultAsynchronous reset, input, active low, internally synchronized.\end_layout\begin_layout SubsectionStream Input\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterstream_data\family default8-bit elementary stream data, input, synchronous with\family typewriterclk\family default, byte aligned.The elementary stream is an MPEG2 4:2:0 video elementary stream.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterstream_valid\family defaultelementary stream data valid, input, synchronous with\family typewriterclk\family default.Assert when stream_data valid.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterbusy\family defaultbusy, active high, output, synchronous with\family typewriterclk\family default.When high, indicates maintaining\family typewriterstream_valid\family defaulthigh will overflow decoder input buffers.\end_layout\begin_layout SubsectionRegister File Access\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterreg_addr\family default5-bit register address, input, synchronous with\family typewriterclk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterreg_dta_in\family default32-bit register data in, input, synchronous with\family typewriterclk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterreg_wr_en\family defaultregister write enable, input, active high, synchronous with\family typewriterclk\family default.Assert to write\family typewriterreg_dta_in\family defaultto\family typewriterreg_addr\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterreg_dta_out\family default32-bit register data out, output, synchronous with\family typewriterclk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterreg_rd_en\family defaultActive high register read enable, input, synchronous with\family typewriterclk\family default.Assert to obtain the contents of register\family typewriterreg_addr\family defaultat\family typewriterreg_dta_out\family default.\end_layout\begin_layout SubsectionMemory Controller\end_layout\begin_layout StandardThe interface between MPEG2 decoder and memory controller consists of twofifos.The memory request FIFO sends memory read, write or refresh requests fromdecoder to memory controller.The memory response FIFO sends data read from memory controller to MPEG2decoder.The data from the memory read requests appears in the memory response FIFOin the same order as the memory reads were issued in the memory requestFIFO.\end_layout\begin_layout SubsectionMemory Request FIFO\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_req_rd_cmd\family defaultmemory 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usebox="none">\begin_inset Text\begin_layout Plain LayoutCMD_WRITE\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutWrite 64-bit word\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Memory-controller-commands"\end_insetMemory controller commands\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_req_rd_addr\family default22-bit memory request address, output, synchronous with\family typewritermem_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_req_rd_dta\family default64-bit memory request data, output, synchronous with\family typewritermem_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_req_rd_en\family defaultmemory request read enable, input, active high, synchronous with\family typewritermem_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_req_rd_valid\family defaultmemory request read valid, output, active high, synchronous with\family typewritermem_clk\family default.Indicates when\family typewritermem_req_rd_cmd\family default,\family typewritermem_req_rd_addr\family defaultand\family typewritermem_req_rd_dta\family defaulthave meaningful values.\end_layout\begin_layout SubsectionMemory Response FIFO\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_res_wr_dta\family default64-bit memory response write data, input, synchronous with\family typewritermem_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_res_wr_en\family defaultmemory response write enable, input, active high, synchronous with\family typewritermem_clk\family default.Assert to write\family typewritermem_res_wr_dta\family defaultto the memory response FIFO.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_res_wr_almost_full\family defaultmemory response write almost full, output, active high, synchronous withmem_clk.When high, indicates maintaining\family typewritermem_res_wr_en\family defaulthigh will overflow the memory response FIFO.The current clock cycle can be completed without overflowing the memoryresponse FIFO.\end_layout\begin_layout SubsectionVideo Output\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterr\family defaultred component, output, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterg\family defaultgreen component, output, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterb\family defaultblue component, output, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritery\family defaultY luminance, output, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriteru\family defaultCr chrominance, output, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterv\family defaultCb chrominance, output, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterpixel_en\family defaultpixel enable, output, active high, synchronous with\family typewriterdot_clk\family default.When\family typewriterpixel_en\family defaultis high,\family typewriterr\family default,\family typewriterg\family default,\family typewriterb\family default,\family typewritery\family default,\family typewriteru\family defaultand\family typewriterv\family defaultare valid; when\family typewriterpixel_en\family defaultis low video is blanked.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterh_sync\family defaulthorizontal synchronization, output, active high, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterv_sync\family defaultvertical synchronization, output, active high, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterc_sync\family defaultcomposite synchronization, output, active low, synchronous with\family typewriterdot_clk\family default.\end_layout\begin_layout SubsectionTest Point\end_layout\begin_layout StandardThe decoder provides a test point for connecting a logic analyzer.The signals available at the test point can be selected either by softwarecontrol, or using dip switches.The signals available at the test point are not defined as part of thisspecification, may vary even for implementations with the same status registerversion number and are subject to change without notice.See Verilog source\family typewriterprobe.v\family defaultfor details.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritertestpoint_dip_en\family default1-bit input.If\family typewritertestpoint_dip_en\family defaultis high, the registers visible at\family typewritertestpoint\family defaultare selected using\family typewritertestpoint_dip\family default.If\family typewritertestpoint_dip_en\family defaultis low, the registers visible at\family typewritertestpoint\family defaultoutput are selected using the\family typewritertestpoint_sel\family defaultfield of register 15.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritertestpoint_dip\family default4-bit input.\family typewritertestpoint_dip\family defaultselects test point output if\family typewritertestpoint_dip_en\family defaultis high.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritertestpoint\family default34-bit output.\family typewritertestpoint\family defaultis a test point to connect a 34-channel logic analyzer probe to the MPEG2decoder.Up to 16 different sets of signals are available, hardware selectable usingthe\family typewritertestpoint_dip\family defaultdip switches or software selectable by writing to register 15.Any clocks present are on bits 32 and/or 33; bits 0 to 31 are data only.Bits 0 to 31 can also be accessed by software, by reading register 15.\end_layout\begin_layout SubsectionStatus\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritererror\family defaulterror, output, active high, synchronous with\family typewriterclk\family default.Indicates variable length decoding encountered an error in the bitstream.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterinterrupt\family defaultinterrupt, output, active high, synchronous with\family typewriterclk\family default.Reading the status register allows software to determine the cause of theinterrupt, and will clear the interrupt.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterwatchdog_rst\family roman\series medium\shape up\size normal\emph off\bar no\noun off\color nonewatchdog-generated reset signal, output, active low,\family default\series default\shape default\size default\emph default\bar default\noun default\color inheritsynchronous with\family typewriterclk\family default.Normally high; low during one clock cycle if the watchdog timer expires.\end_layout\begin_layout SectionProcessor Tasks\end_layout\begin_layout StandardTo decode an MPEG-2 bitstream, the processor should execute the followingtasks, in order:\end_layout\begin_layout EnumerateInitialize the horizontal, horizontal sync, vertical, vertical sync andvideo mode registers with reasonable defaults.Clear\family typewriterosd_enable\family default,\family typewriterpicture_hdr_intr_en\family defaultand\family typewriterframe_end_intr_en\family default.Set the\family typewritervideo_ch_intr_en\family defaultflag.\end_layout\begin_layout EnumerateStart feeding the MPEG-2 bitstream to the\family typewriterstream_data\family defaultport of the decoder.\end_layout\begin_layout EnumerateThe decoder will issue an interrupt when video resolution or frame ratechanges.Whenever the decoder issues an interrupt, clear the interrupt by readingthe status register.Read the size, display size and frame rate registers.Calculate a new modeline, change dot clock frequency if necessary, andwrite the new video timing parameters to the horizontal, horizontal sync,vertical, vertical sync and video mode registers.\end_layout\begin_layout EnumerateAt bitstream end, pad the stream with 8 times hex 000001b7, the sequenceend code (ISO/IEC 13818-2, par.6.2.1, Start Codes).\end_layout\begin_layout StandardIf the On-Screen Display (OSD) is used, the processor should execute thefollowing tasks as well:\end_layout\begin_layout EnumerateInitialize the On-Screen Display color look-up table.\end_layout\begin_layout EnumerateWait until\family typewriterhorizontal_size\family defaultand\family typewritervertical_size\family defaulthave meaningful values.\end_layout\begin_layout EnumerateWrite to the On-Screen Display.\end_layout\begin_layout EnumerateSet\family typewriterosd_enable\family defaultto one.\end_layout\begin_layout EnumerateIf a video change interrupt occurs, and\family typewriterhorizontal_size\family defaultor\family typewritervertical_size\family defaulthas changed, rewrite the On-Screen Display.\end_layout\begin_layout StandardWriting to the OSD is described in detail\begin_inset CommandInset refLatexCommand vpagerefreference "sec:On-Screen-Display"\end_inset.Interrupt handling is treated\begin_inset CommandInset refLatexCommand vpagerefreference "sec:Interrupts"\end_inset.\end_layout\begin_layout SectionRegisters\end_layout\begin_layout StandardThe processor interface to the decoder consists of two times 16 32-bit registers.These registers can be divided in 16 read-mode registers (Table\begin_inset CommandInset refLatexCommand refreference "tab:Read-mode-Registers"\end_inset) and 16 write-mode registers (Table\begin_inset CommandInset refLatexCommand refreference "tab:Write-mode-Registers"\end_inset).The read-mode registers allow reading decoder status, while the write-moderegisters allow setting video timing parameters and writing to the On-ScreenDisplay (OSD).\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="21" columns="5"><features tabularvalignment="middle"><column alignment="center" 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Layout31-0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterosd_dta_low\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row endhead="true" endfirsthead="true"><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layouta\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutosd_addr\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout31-29\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterosd_frame\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout28-27\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterosd_comp\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout26-16\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterosd_addr_x\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout10-0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterosd_addr_y\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutb\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layouttrick mode\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout10\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterdeinterlace\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout9-5\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterrepeat_frame\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout4\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterpersistence\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout3-1\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewritersource_select\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterflush_vbuf\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutf\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layouttestpoint\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout3-0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewritertestpoint_sel\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutw\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Write-mode-Registers"\end_insetWrite-mode Registers\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout SectionRead-only Registers\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterversion\family defaultcontains a non-zero FPGA bitstream (hardware) version number.Software should at least print a warning\family typewriter\begin_inset Quotes eld\end_insetWarning: hardware version (%i.%i) more recent than software driver\begin_inset Quotes erd\end_inset\family defaultif the hardware version is higher than expected.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterpicture_hdr\family defaultis set whenever an picture header is encountered in the bitstream.\family typewriterpicture_hdr\family defaultis cleared whenever the status register is read.In a well-behaved MPEG-2 stream,\family typewriterhorizontal_size\family default,\family typewritervertical_size\family default,\family typewriterdisplay_horizontal_size\family default,\family typewriterdisplay_vertical_size, aspect_ratio_information\family defaultand\family typewriterframe_rate\family defaultwill have meaningful values when a picture header is encountered.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterframe_end\family defaultis set when video vertical synchronization begins.\family typewriterframe_end\family defaultis cleared whenever the status register is read.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritervideo_ch\family defaultis set whenever video resolution or frame rate changes.\family typewritervideo_ch\family defaultis cleared whenever the status register is read.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritererror\family defaultis set when variable length decoding cannot parse the bitstream.\family typewritererror\family defaultis cleared whenever the status register is read.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterwatchdog_status\family defaultis high if the watchdog timer expired.\family typewriterwatchdog_status\family defaultis cleared whenever the status register is read.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterhorizontal_size\family defaultis defined in ISO/IEC 13818-2, par.6.2.2.1, par.6.3.3.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritervertical_size\family defaultis defined in ISO/IEC 13818-2, par.6.2.2.1, par.6.3.3.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterdisplay_horizontal_size\family defaultis defined in ISO/IEC 13818-2, par.6.2.2.4, par.6.3.6.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterdisplay_vertical_size\family defaultis defined in ISO/IEC 13818-2, par.6.2.2.4, par.6.3.6.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriteraspect_ratio_information\family defaultis defined in ISO/IEC 13818-2, par.6.3.3.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermatrix_coefficients\family defaultis defined in ISO/IEC 13818-2, par.6.3.6.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterframe_rate_extension_n\family defaultis defined in ISO/IEC 13818-2, par.6.3.3, par.6.3.5.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterframe_rate_code\family defaultis defined in ISO/IEC 13818-2, par.6.3.3, Table 6-4.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterprogressive_sequence\family defaultis defined in ISO/IEC 13818-2, par.6.3.5.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterframe_rate_extension_d\family defaultis defined in ISO/IEC 13818-2, par.6.3.3, par.6.3.5.\end_layout\begin_layout SectionOn-Screen Display\end_layout\begin_layout Standard\begin_inset CommandInset labelLatexCommand labelname "sec:On-Screen-Display"\end_insetThe OSD has the same resolution and aspect ratio as the MPEG-2 video beingdisplayed.If no MPEG-2 video is being displayed, the OSD is undefined.Note feeding the decoder a simple MPEG-2 sequence header with\family typewriterhorizontal_size\family defaultand\family typewritervertical_size\family defaultalready satisfies the requirements for using the OSD.\end_layout\begin_layout StandardThe OSD is only shown if there is video output.If one wishes to display an OSD when no MPEG2 video is being reproduced,video output can be forced by setting\family typewritersource_select\family defaultto 4, 5, 6 or 7.\begin_inset Separator latexpar\end_inset\end_layout\begin_layout StandardThe OSD may use up to 256 different colors.The OSD color lookup table (CLT) stores\family typewritery\family default,\family typewriteru\family default,\family typewriterv\family defaultand\family typewriterosd_clt_mode\family defaultdata for each color.The\family typewritery\family default,\family typewriteru\family defaultand\family typewriterv\family defaultvalues are interpreted as defined by\family typewritermatrix_coefficients\family default.The\family typewriterosd_clt_mode\family defaultvalue determines the color displayed according to Table\begin_inset CommandInset refLatexCommand refreference "tab:On-Screen-Display-Modes"\end_inset.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="24" columns="2"><features tabularvalignment="middle"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutosd_clt_mode\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutComment\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00000\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 0/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00001\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 1/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00010\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 2/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00011\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 3/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00100\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 4/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00101\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 5/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00110\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 6/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx00111\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 7/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01000\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 8/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01001\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 9/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01010\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 10/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01011\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 11/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01100\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 12/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01101\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 13/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01110\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 14/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx01111\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 15/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxxx11111\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha = 16/16\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxx0xxxxx\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutattenuate video pixel by alpha\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutxx1xxxxx\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutalpha blend osd and video pixel\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout00xxxxxx\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutdisplay video pixel\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout01xxxxxx\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutdisplay attenuated/alpha blended pixel\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout10xxxxxx\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutdisplay osd pixel\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout11xxxxxx\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutdisplay blinking osd pixel\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:On-Screen-Display-Modes"\end_insetOn-Screen Display Modes\end_layout\end_inset\end_layout\end_insetThe different modes combine osd and video in various ways:\end_layout\begin_layout Itemizevideo.This is the normal mode of operation.\end_layout\begin_layout Itemizeattenuated video.16 discrete levels of attenuation can be used to fade video in or out.\end_layout\begin_layout Itemizeon-screen display.\end_layout\begin_layout Itemizeblend of on-screen display and video.16 discrete levels of translucency.\end_layout\begin_layout Itemizeblinking on-screen display.Alternates between osd pixel and attenuated/alpha blended video pixel witha frequency of about one second.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterosd_enable\family defaultdetermines whether the On-Screen Display is shown or not.If\family typewriterosd_enable\family defaultis low, the On-Screen Display is not shown.If\family typewriterosd_enable\family defaultis high, the On-Screen Display is shown.The osd color lookup table has to be initialized and the osd has to bewritten before\family typewriterosd_enable\family defaultis raised.\family typewriterosd_enable\family defaultis 0 on power-up or reset.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterosd_wr_en\family defaultis set whenever an osd write is has been accepted, whether the osd writewas successful or not.\family typewriterosd_wr_en\family defaultis cleared whenever the status register is read.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterosd_wr_ack\family defaultis set whenever an osd write has been successful.\family typewriterosd_wr_ack\family defaultis cleared whenever the status register is read.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterosd_wr_full\family defaultis set when the osd write fifo is full.When the osd write fifo is full, osd writes are not accepted.\end_layout\begin_layout StandardWhen writing to the osd color lookup table:\end_layout\begin_layout EnumerateWrite\family typewriterosd_clt_yuvm.\end_layout\begin_layout EnumerateWrite\family typewriterosd_clt_addr.\end_layout\begin_layout StandardWrites to the osd color lookup table take effect immediately.\end_layout\begin_layout StandardWhen writing to the osd:\end_layout\begin_layout EnumerateOnly write to the osd when\family typewriterhorizontal_size\family defaultand\family typewritervertical_size\family defaulthave meaningful values.This is the case when a picture header has been encountered.\end_layout\begin_layout EnumerateVerify\family typewriterosd_wr_full\family defaultis low.Writing when\family typewriterosd_wr_full\family defaultis high has no effect.\end_layout\begin_layout EnumerateWrite the leftmost four pixels to\family typewriterosd_dta_high\family default.\end_layout\begin_layout EnumerateWrite the rightmost four pixels to\family typewriterosd_dta_low.\end_layout\begin_layout EnumerateWrite x and y position of the leftmost pixel to\family typewriterosd_addr\family default.Note x has to be a multiple of 8.\family typewriterosd_frame\family defaultalways has value 4 for OSD writes.\family typewriterosd_comp\family defaultalways has value 0 for OSD writes.\end_layout\begin_layout EnumerateRead the status register until\family typewriterosd_wr_en\family defaultis asserted.When\family typewriterosd_wr_en\family defaultis high, the value of\family typewriterosd_wr_ack\family defaultindicates whether the write was successful.\end_layout\begin_layout StandardWrites to the osd pass through a 32-position fifo.This introduces some latency.Repeating the last osd write 32 times flushes fifo contents, ensuring osdmemory has been updated.\end_layout\begin_layout SectionFrame Store\end_layout\begin_layout StandardPixels can be written directly to the frame store, using the same mechanismas OSD writes.By writing pixels to the frame store and afterwards setting the\family typewritersource_select\family defaultfield of the trick register (described\begin_inset CommandInset refLatexCommand vpagerefreference "sec:Trick-mode"\end_inset) arbitrary bitmaps can be shown.\begin_inset Separator latexpar\end_inset\end_layout\begin_layout StandardThe only difference between an OSD write and a frame store write is thevalue of\family typewriterosd_frame\family defaultand/or\family typewriterosd_comp\family default.Tables\begin_inset CommandInset refLatexCommand refreference "tab:OSD-Frame"\end_insetand\begin_inset CommandInset refLatexCommand refreference "tab:OSD-Component"\end_insetlist the frame and component codes.Frames 0 and 1 are used for storing I and P frames.Frames 2 and 3 are used for storing B frames.All frames are stored in 4:2:0 format, with u and v frames having halfthe width and height of the y frame.Note y, u and v values are stored in memory with an offset of 128.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="6" columns="2"><features tabularvalignment="middle"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutosd_frame\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFrame\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout0\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout3\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout3\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout4\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutOSD\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:OSD-Frame"\end_insetOSD Frame\end_layout\end_inset\begin_inset Separator latexpar\end_inset\end_layout\end_inset\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="4" columns="2"><features tabularvalignment="middle"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutosd_comp\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutComponent\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layouty\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutu\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutv\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:OSD-Component"\end_insetOSD Component\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout StandardWrites to the frame store are only defined when\family typewriterhorizontal_size\family defaultand\family typewritervertical_size\family defaulthave meaningful values.Writes with\family typewriterosd_frame\family default4 are only defined when\family typewriterosd_comp\family defaultis 0.\end_layout\begin_layout Section\begin_inset CommandInset labelLatexCommand labelname "sec:Video-Modeline"\end_insetVideo Modeline\end_layout\begin_layout StandardThe video timing parameters are:\end_layout\begin_layout Itemize\family typewriterhorizontal_resolution\end_layout\begin_layout Itemize\family typewriterhorizontal_sync_start\end_layout\begin_layout Itemize\family typewriterhorizontal_sync_end\end_layout\begin_layout Itemize\family typewriterhorizontal_length\end_layout\begin_layout Itemize\family typewritervertical_resolution\end_layout\begin_layout Itemize\family typewritervertical_sync_start\end_layout\begin_layout Itemize\family typewritervertical_sync_end\end_layout\begin_layout Itemize\family typewritervertical_length\end_layout\begin_layout Itemize\family typewriterhorizontal_halfline\end_layout\begin_layout Itemize\family typewriterinterlaced\end_layout\begin_layout Itemize\family typewriterpixel_repetition\end_layout\begin_layout StandardThese parameters can be deduced from the X11 modeline for the display, whichis described in the\begin_inset Quotes eld\end_insetXFree86 Video Timings HOWTO\begin_inset Quotes erd\end_inset.Writing to the internal registers which contain the video timing parameterswill restart the video synchronization generator.\end_layout\begin_layout StandardTwo video timing diagrams are shown, one for progressive video (Figure\begin_inset CommandInset refLatexCommand refreference "fig:Progressive-Video"\end_inset) and one for interlaced video (Figure\begin_inset CommandInset refLatexCommand refreference "fig:Interlaced-Video"\end_inset).The diagrams show the picture area (a light grey rectangle), flanked byhorizontal sync (a dark grey vertical bar) and vertical sync (a dark greyhorizontal bar).\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Graphicsfilename progressive.epswidth 100line%keepAspectRatio\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:Progressive-Video"\end_insetProgressive Video\end_layout\end_inset\begin_inset Separator latexpar\end_inset\end_layout\end_inset\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\noindent\align center\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Graphicsfilename interlaced.epswidth 100line%keepAspectRatioBoundingBox 0bp 0bp 495bp 484bpclip\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:Interlaced-Video"\end_insetInterlaced Video\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterhorizontal_resolution\family defaultnumber of dots per scan line.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterhorizontal_sync_start\family defaultused to specify the horizontal position the horizontal sync pulse begins.The leftmost pixel of a line has position zero.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterhorizontal_sync_end\family defaultused to specify the horizontal position the horizontal sync pulse ends.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterhorizontal_length\family defaulttotal length, in pixels, of one scan line.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritervertical_resolution\family defaultnumber of visible lines per frame (progressive) or field (interlaced).\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritervertical_sync_start\family defaultused to specify the line number within the frame (progressive) or field(interlaced) the vertical sync pulse begins.The topmost line of a frame or field is line number zero.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritervertical_sync_end\family defaultused to specify the line number within the frame (progressive) or field(interlaced) the vertical sync pulse ends.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterhorizontal_halfline\family defaultused to specify the horizontal position the vertical sync begins on oddfields of interlaced video.Not used in progressive mode.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritervertical_length\family defaulttotal number of lines of a vertical frame (progressive) or field (interlaced).\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterclip_display_size\family defaultIf asserted, the image is clipped to (\family typewriterdisplay_horizontal_size\family default,\family typewriterdisplay_vertical_size\family default).If not asserted, the image is clipped to (\family typewriterhorizontal_size\family default,\family typewritervertical_size\family default).\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterinterlaced\family defaultused to specify interlaced output is required.If\family typewriterinterlaced\family defaultis asserted, vertical sync is delayed one-half scan line at the end ofodd fields.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterpixel_repetition\family defaultIf\family typewriterpixel_repetition\family defaultis asserted, each pixel is output twice.This can be used if the original dot clock is too low for the transmitter.As an example, suppose valid dot clock rates are 25\SpecialChar ldots165 MHz, but the SDTVvideo being decoded has a dot clock of only 13.5 MHz.Asserting\family typewriterpixel_repetition\family defaultand doubling dot clock frequency results in a dot clock of 27 MHz, sufficientfor SDTV video to be transmitted across the link.\end_layout\begin_layout SectionInterrupts\end_layout\begin_layout Standard\begin_inset CommandInset labelLatexCommand labelname "sec:Interrupts"\end_insetThree independent conditions may trigger an interrupt: when a picture headeris encountered in the bitstream, when frame display ends, and when videoresolution or frame rate changes.All three interrupt sources are optional and can be disabled individually.\end_layout\begin_layout StandardWhen\family typewriterpicture_hdr_intr_en\family defaultis high and a picture header is encountered in the bitstream,\family typewriterpicture_hdr\family defaultis set and the interrupt signal is asserted until the status register isread.If\family typewriterpicture_hdr_intr_en\family defaultis low, the interrupt signal is never raised.\family typewriterpicture_hdr and picture_hdr_intr_en\family defaultare 0 on power-up or reset.The picture header interrupt marks the\begin_inset Quotes eld\end_insetheartbeat\begin_inset Quotes erd\end_insetof the video decoding engine.\end_layout\begin_layout StandardWhen video vertical synchronization begins and\family typewriterframe_end_intr_en\family defaultis high,\family typewriterframe_end\family defaultis set and the interrupt signal is asserted until the status register isread.If\family typewriterframe_end_intr_en\family defaultis low, the interrupt signal is never raised.\family typewriterframe_end and frame_end_intr_en\family defaultare 0 on power-up or reset.The frame end interrupt marks the\begin_inset Quotes eld\end_insetheartbeat\begin_inset Quotes erd\end_insetof the video display engine.\end_layout\begin_layout StandardWhen one of\family typewriterhorizontal_size, vertical_size, display_horizontal_size, display_vertical_size,progressive_sequence, aspect_ratio_information, frame_rate_code, frame_rate_extension_n,\family defaultor\family typewriterframe_rate_extension_d\family defaultchanges, and\family typewritervideo_ch_intr_en\family defaultis high,\family typewritervideo_ch\family defaultis set and the interrupt signal is asserted until the status register isread.If\family typewritervideo_ch_intr_en\family defaultis low, the interrupt signal is never raised.\family typewritervideo_ch\family defaultand\family typewritervideo_ch_intr_en\family defaultare 0 on power-up or reset.The video change interrupt marks an abrupt change in the MPEG2 bitstream.\end_layout\begin_layout StandardIt is suggested that software, when receiving a video change interrupt:\end_layout\begin_layout EnumerateReads the size, display size and frame rate registers.\end_layout\begin_layout EnumerateIf\family typewriterframe_rate_code\family default,\family typewriterframe_rate_extension_d\family defaultor\family typewriterframe_rate_extension_n\family defaulthave changed, change dot clock frequency.\end_layout\begin_layout EnumerateCalculates a video modeline, either using a look-up table or algebraically,e.g.using the VESA General Timing Formula.\end_layout\begin_layout EnumerateWrites the new video modeline parameters to the horizontal, horizontal sync,vertical, vertical sync and video mode registers.This restarts the video synchronization.\end_layout\begin_layout EnumerateIf\family typewriterhorizontal_size\family defaultor\family typewritervertical_size\family defaulthave changed and\family typewriterosd_enable\family defaultis high, rewrite the On-Screen Display.\end_layout\begin_layout SectionWatchdog\end_layout\begin_layout StandardThe MPEG2 decoder contains a watchdog circuit.The watchdog circuit resets the decoder if the decoder is unresponsive.The decoder is considered unresponsive if the decoder does not accept MPEG2data for a period of time longer than the watchdog timeout interval.We outline how to configure the watchdog timeout interval, define underwhich conditions the watchdog circuit activates, and describe what happenswhen the watchdog timer expires.\end_layout\begin_layout StandardThe watchdog timeout interval can be configured by writing\family typewriterwatchdog_interval\family default, register 0, bits 15-8.\end_layout\begin_layout Itemizewriting 0 to\family typewriterwatchdog_interval\family defaultcauses the watchdog timer to expire immediately.\end_layout\begin_layout Itemizewriting a value from 1 to 254, inclusive, to\family typewriterwatchdog_interval\family defaultenables the watchdog circuit.\end_layout\begin_layout Itemizewriting 255 decimal to\family typewriterwatchdog_interval\family defaultdisables the watchdog circuit.\end_layout\begin_layout StandardThe default value of\family typewriterwatchdog_interval\family defaultis 127.If\family typewriterwatchdog_interval\family defaulthas a value from 1 to 254, inclusive, the watchdog timeout is\begin_inset Formula\[watchdog\_timeout=(watchdog\_interval+1).(repeat\_frame+1).2^{18}\]\end_inset\family typewriterclk\family defaultclock cycles.\family typewriterrepeat_frame\family default(Section\begin_inset CommandInset refLatexCommand refreference "sec:Trick-mode"\end_inset) determines the numer of times a decoded video frame is displayed.Each decoded video image is shown\family typewriterrepeat_frame\family default\begin_inset space ~\end_inset+\begin_inset space ~\end_inset1 times.If a video frame is shown n times, the watchdog timeout is multiplied byn as well.This implies there is no need to adjust the watchdog timer if video isreproduced in slow motion.\end_layout\begin_layout StandardThe default value of\family typewriterrepeat_frame\family defaultis 0.If decoder\family typewriterclk\family defaultfrequency is 75 MHz the default watchdog timeout interval is 0.45 seconds.\end_layout\begin_layout StandardThe watchdog timer starts running when the decoder raises the\family typewriterbusy\family defaultsignal.If the\family typewriterbusy\family defaultsignal remains high for longer than the watchdog timeout interval, a resetis generated.\end_layout\begin_layout StandardThe watchdog timer is reset\end_layout\begin_layout Itemizewhen the global\family typewriterrst\family defaultinput signal is driven low\end_layout\begin_layout Itemizewhen the decoder\family typewriterbusy\family defaultsignal is low\end_layout\begin_layout Itemizewhen the decoder has been halted to show the current frame (\family typewriterrepeat_frame\family defaultis 31,\shape italicfreeze-frame\shape default)\end_layout\begin_layout Itemizewhen the decoder has been halted to show a particular framestore frame (\family typewritersource_select\family defaultis non-zero)\end_layout\begin_layout Itemizewhen the watchdog circuit has been disabled (\family typewriterwatchdog_interval\family defaulthas been set to 0 or to 255)\end_layout\begin_layout Itemizeduring the first\begin_inset Formula $2^{26}$\end_inset\family typewriterclk\family defaultclock cycles after the watchdog timer expired, or the decoder was reset.This watchdog timer\shape italicholdoff\shape defaultdisables the watchdog during system initialisation.If clock frequency is 75 MHz,\begin_inset Formula $2^{26}$\end_insetclock cycles corresponds to 0.89 seconds.\end_layout\begin_layout StandardWhen the watchdog timer expires\end_layout\begin_layout Itemizethe\family typewriterwatchdog_rst\family defaultoutput pin becomes low during one\family typewriterclk\family defaultclock cycle.The\family typewriterwatchdog_rst\family defaultoutput can be used to reset external hardware, or to generate a processorinterrupt.\end_layout\begin_layout Itemizethe\family typewriterwatchdog_status\family defaultbit in the status register is set to 1.Software can detect whether the watchdog timer expired by checking\family typewriterwatchdog_status\family defaultin the status register.Reading the status register resets the\family typewriterwatchdog_status\family defaultbit back to 0.\end_layout\begin_layout ItemizeThe framestore, On-Screen Display and circular video buffer are filled withzeroes.\end_layout\begin_layout Itemizeany data in the memory response fifo is discarded.\end_layout\begin_layout Itemize\family typewriterosd_enable\family defaultis set to 0.This disables the On-Screen Display, as the On-Screen Display now containsall zeroes.\end_layout\begin_layout Itemizeconfiguration data written to the register file is\series boldnot\series defaultmodified when the watchdog expires.In particular, the video timing parameters (Sec.\begin_inset CommandInset refLatexCommand refreference "sec:Video-Modeline"\end_inset) remain unchanged.\end_layout\begin_layout StandardThe\family typewriterwatchdog_rst\family defaultoutput pin can optionally be used to reset external hardware when the watchdogexpires.Examples of external hardware are the memory controller and the DVI dotclock generator.Note, however, resetting memory controller and DVI dot clock generatorwhen the watchdog timer expires is optional.\end_layout\begin_layout StandardThe MPEG2 decoder does not require the external memory controller to bereset when the watchdog timer expires.When the watchdog timer expires, the MPEG2 decoder will write zeroes toall addresses from FRAME_0_Y to VBUF_END (\family typewriterframestore_request.v\family default, STATE_CLEAR).When the watchdog timer expires, the MPEG2 decoder will also read and discardany data from the memory response fifo (\family typewriterframestore_response.v\family default, STATE_FLUSH).These two actions re-synchronize MPEG2 decoder and external memory controllerand bring memory to a known state.\end_layout\begin_layout StandardThe MPEG2 decoder also does not require the DVI clock generator to be resetwhen the watchdog expires.When the watchdog timer expires, the video timing parameters (Sec.\begin_inset CommandInset refLatexCommand refreference "sec:Video-Modeline"\end_inset) remain unchanged.If the DVI clock frequency remains unchanged when the watchdog timer expires,the decoder will continue with exactly the same video timing.\end_layout\begin_layout SectionTrick mode\end_layout\begin_layout Standard\begin_inset CommandInset labelLatexCommand labelname "sec:Trick-mode"\end_insetThe trick mode register provides a toolbox for implementing non-standardplayback modes.An example of a non-standard playback mode is slow motion.It is perhaps easiest to visualize trick mode settings as a pipeline (Figure\begin_inset CommandInset refLatexCommand refreference "fig:Trick-mode-pipeline"\end_inset).\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Graphicsfilename trick_mode.epslyxscale 50scale 60clip\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:Trick-mode-pipeline"\end_insetTrick mode pipeline\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterflush_vbuf\family defaultWriting one to\family typewriterflush_vbuf\family defaultclears the incoming video buffer.Flushing the video buffer may be useful when changing channels.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterpersistence\family defaultIf\family typewriterpersistence\family defaultis set, and no new decoded image is available at frame start the last decodedimage is shown again.If\family typewriterpersistence\family defaultis not set, and no new decoded image is available at frame start a blankscreen is shown.\family typewriterpersistence\family defaultis 1 on power-up or reset.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritersource_select\family defaultIf zero, normal video is shown.Non-zero values allow continuous output of a blank screen, or a specificframe from the frame store, as in table\begin_inset CommandInset refLatexCommand refreference "tab:Source-Select"\end_inset.\family typewritersource_select\family defaultis 0 on power-up or reset.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="7" columns="2"><features tabularvalignment="middle"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutsource_select\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFrame shown\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutlast decoded frame\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutblank screen\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout4\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutframe 0\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout5\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutframe 1\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout6\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutframe 2\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout7\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutframe 3\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Source-Select"\end_insetSource Select\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterrepeat_frame\family defaultIf zero, each decoded image is shown once.If non-zero, contains the number of times the decoded image will be additionally shown, as in table\begin_inset CommandInset refLatexCommand refreference "tab:Repeat-Frame"\end_inset.A value of 31 shows the image indefinitely.\family typewriterrepeat_frame\family defaultis 0 on power-up or reset.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="7" columns="2"><features tabularvalignment="middle"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutrepeat_frame\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layouttimes shown\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout0\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout3\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\SpecialChar ldots\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout30\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout31\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout31\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layoutforever\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Repeat-Frame"\end_insetRepeat Frame\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterdeinterlace\family defaultSetting\family typewriterdeinterlace\family defaulthigh forces the decoder to output video as frames, even if the MPEG2 streamis interlaced.This can be used to reproduce interlaced MPEG2 streams on progressive displays.Setting\family typewriterdeinterlace\family defaultis not recommended when reproducing a progressive MPEG2 stream on a progressivedisplay.Setting\family typewriterdeinterlace\family defaulthas no effect if the video modeline specifies interlaced output (\family typewriterinterlaced\family defaultset).Note no spatial or temporal interpolation is done (\begin_inset Quotes eld\end_insetweaving\begin_inset Quotes erd\end_inset).\end_layout\begin_layout SectionTest point\end_layout\begin_layout StandardThe MPEG2 decoder provides a test point for connecting a logic analyzer.Internally, the decoder contains various test points, only one of whichis actually output to the logic analyzer.Which internal test point is output to the logic analyzer is determinedby the contents of\family typewritertestpoint_sel\family default.The value of bits 0..31 of the test point can also be read by software.While this is no substitute for a logic analyzer, it is recognized thatin many cases this may be the only option available.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritertestpoint_sel\family defaultUsed in hardware debugging.Determines which internal test point is multiplexed to the 34-channellogical analyzer test point.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritertestpoint\family defaultUsed in hardware debugging.Provides the current value of bits 0 to 31 of the 34-channel logical analyzertest point.\end_layout\begin_layout Chapter\begin_inset CommandInset labelLatexCommand labelname "cha:Decoder-Sources"\end_insetDecoder Sources\end_layout\begin_layout StandardChapter\begin_inset CommandInset refLatexCommand refreference "cha:Decoder-Sources"\end_insetprovides an overview of the decoder sources for the hardware engineer whowishes to synthesize or modify the decoder.\end_layout\begin_layout SectionSource Directory Structure\end_layout\begin_layout StandardThe source files are organized in directories as follows:\end_layout\begin_layout Standard\begin_inset Tabular<lyxtabular version="3" rows="8" columns="3"><features tabularvalignment="middle"><column alignment="left" valignment="top"><column alignment="left" valignment="top"><column alignment="left" valignment="top"><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterbench/\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriteriverilog\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutIcarus behavioral simulation, page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:Icarus-Verilog-Simulation"\end_inset\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterdoc/\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutDocumentation\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterrtl/\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewritermpeg2\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutMPEG2 decoder, page\begin_inset CommandInset refLatexCommand pagerefreference "sec:MPEG2-Decoder"\end_inset\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewritertools/\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterfsmgraph\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutFinite state machine graphs, page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:FSM-Graphs"\end_inset\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterieee1180\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutIEEE1180 IDCT accuracy test, page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:IEEE-1180-IDCT"\end_inset\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterlogicport\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutLogicport logic analyzer, page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:Logicport-Logic-Analyzer"\end_inset\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewritermpeg2dec\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutReference MPEG2 decoder, page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:mpeg2decode"\end_inset\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterstreams\end_layout\end_inset</cell><cell alignment="center" valignment="top" usebox="none">\begin_inset Text\begin_layout Plain LayoutMPEG2 test streams, page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:MPEG2-Test-Streams"\end_inset\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout StandardA linux system with Icarus Verilog is suggested, but not required, as development environment.\end_layout\begin_layout Section\begin_inset CommandInset labelLatexCommand labelname "sec:MPEG2-Decoder"\end_insetMPEG2 Decoder\end_layout\begin_layout StandardThe\family typewriterrtl/mpeg2\family defaultdirectory contains the sources of the MPEG2 decoder itself.This section describes the changes most likely to be needed when instantiatingthe decoder: changing default modeline, changing FIFO sizes, choosing dual-ported ram and fifo models, changing memory mapping.In addition, references are provided for the IDCT and bilinear chroma upsampling algorithms.\end_layout\begin_layout SubsectionFIFO sizes\end_layout\begin_layout StandardFifo depth and almost full/almost empty thresholds are defined in\family typewriterfifo_size.v\family default.Note setting fifo depths and thresholds to arbitrary values can resultin decoder deadlock.\end_layout\begin_layout StandardFigure\begin_inset CommandInset refLatexCommand refreference "fig:MPEG2-decoder-dataflow"\end_insetshows MPEG2 decoder data flow.Together,\family typewriterframestore_request\family default, memory controller and\family typewriterframestore_response\family defaultimplement the framestore.Communication with the framestore is through fifos.The incoming MPEG2 stream is written to\family typewritervbuf_write_fifo\family default.\family typewriterframestore_request\family defaultreads the stream from\family typewritervbuf_write_fifo\family defaultand writes it to the circular video buffer in memory.If\family typewritervbuf_read_fifo\family defaultis almost empty,\family typewriterframestore_request\family defaultissues memory read requests for the circular video buffer.\family typewriterframestore_response\family defaultreceives data from the circular video buffer and writes the data to\family typewritervbuf_read_fifo\family default.The net result is\family typewritervbuf_write_fifo\family default, circular video buffer and\family typewritervbuf_read_fifo\family defaultacting as a single, huge fifo.\end_layout\begin_layout StandardVariable-length decoding reads the MPEG2 stream from\family typewritervbuf_read_fifo\family default, and produces motion vectors and run/length codes.Run/length decoding, inverse quantizing, inverse zig-zag and inverse discretecosine transform (IDCT) read the run/length codes and produce the predictionerror.The prediction error is written to\family typewriterpredict_err_fifo\family default, one row of eight pixels at a time.\end_layout\begin_layout StandardMotion compensation address generation\family typewritermotcomp_addrgen\family defaulttranslates the motion vectors into three sets of memory addresses: theaddresses where the forward motion compensation pixels can be read, theaddresses where the backward motion compensation pixels can be read, andthe addresses where the reconstructed pixels can be written.The addresses of the pixels needed for forward and backward motion compensationare written to the\family typewriterfwd_reader\family defaultand\family typewriterbwd_reader\family defaultaddress fifos.The address of the reconstructed pixels is written to the motion compensationdestination fifo,\family typewriterdst_fifo\family default.The memory subsystem reads the\family typewriterfwd_reader\family defaultand\family typewriterbwd_reader\family defaultaddress fifos, and writes the pixel values to the\family typewriterfwd_reader\family defaultand\family typewriterbwd_reader\family defaultdata fifos.\end_layout\begin_layout StandardMotion compensation reconstruction\family typewritermotcomp_recon\family defaultadds pixel values read from forward motion compensation data fifo, backwardmotion compensation data fifo and prediction error, and writes the resultto the address read from the motion compensation destination fifo.\begin_inset Separator latexpar\end_inset\end_layout\begin_layout StandardDisplaying the video image requires chroma resampling and yuv to rgb conversion.Resampling address generation\family typewriterresample_addrgen\family defaultscans the reconstructed video image, line by line.The addresses of the pixels are written to the\family typewriterdisp_reader\family defaultaddress fifo.The memory subsystem reads the addresses from\family typewriterdisp_reader\family defaultaddress fifo and writes the pixel values to the\family typewriterdisp_reader\family defaultdata fifo.\family typewriterresample_dta\family defaultreads the pixel values from the\family typewriterdisp_reader\family defaultdata fifo, while\family typewriterresample_bilinear\family defaultdoes the actual bilinear chroma upsampling calculations.After conversion from yuv to rgb, the pixels are written to the pixel queue\family typewriterpixel_queue\family defaultwhich adapts between decoder and DVI clocks.\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Graphicsfilename fifos.pslyxscale 33height 90theight%\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:MPEG2-decoder-dataflow"\end_insetMPEG2 decoder dataflow\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout StandardNote the memory tag fifo\family typewritermem_tag_fifo\family defaultbetween\family typewriterframestore_request\family defaultand\family typewriterframestore_response\family default.For every memory read request,\family typewriterframestore_request\family defaultwrites a tag to the memory tag fifo.The tag identifies the source of the memory read request: circular videobuffer, forward and backward motion compensation, or resampling.For every data word received from memory,\family typewriterframestore_response\family defaultreads a tag from the memory tag fifo, and writes the data word receivedfrom memory to the data fifo corresponding to the tag.If the memory tag fifo is almost full,\family typewriterframestore_request\family defaultstops issuing memory read or write requests.As a result, the number of outstanding memory read requests is always lessthan or equal to the size of the memory tag fifo.\end_layout\begin_layout StandardWhen modifying\family typewriterfifo_size.v\family default, care should be taken the fifos can never overflow.Note that when\family typewriterframestore_request\family defaultstops issuing memory read requests, there still may be outstanding memoryread requests in the memory request queue.The number of outstanding memory read requests is always smaller than,or equal to, the size of the memory tag fifo.When modifying\family typewriterfifo_size.v\family default, remember fifos which receive data from memory may receive outstandingdata, even after\family typewriterframestore_request\family defaulthas stopped sending memory read requests.\end_layout\begin_layout SubsectionDual-ported memory and FIFO models\end_layout\begin_layout StandardFPGAs typically provide dedicated on-chip fifo's and dual-port RAMs.The designer then has to choose between using vendor-provided FIFOs anddual-port RAMs or writing his own.\end_layout\begin_layout StandardThe file\family typewriterwrappers.v\family defaultdefines the implementation of all dual-port RAMs and fifos in the design.For each component, two versions are provided: one where read and writeport share a common clock; and one where read and write port have independentclocks.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterdpram_sc\family defaultdual-ported ram, same clock for read and write ports\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterdpram_dc\family defaultdual-ported ram, different clock for read and write ports\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterfifo_sc\family defaultfifo, same clock for read and write ports\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterfifo_dc\family defaultfifo, different clock for read and write ports\end_layout\begin_layout StandardThe dual-ported rams are inferred from code in\family typewriterwrappers.v\family default.The fifos can be either implemented in Verilog, or instantiated as FPGAprimitives, depending upon\family typewriterwrappers.v\family default.Following fifo models are available:\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterxfifo_sc.v\family defaultfifo, same clock for read and write port.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritergeneric_fifo_sc_b.v\family defaultOpenCores generic fifo, different clock for read and write ports.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterxilinx_fifo_sc.v\family defaultXilinx Virtex-5 fifo, same clock for read and write ports.Uses\family typewriterxilinx_fifo.v\family default,\family typewriterxilinx_fifo144.v\family defaultand\family typewriterxilinx_fifo216.v\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterxilinx_fifo_dc.v\family defaultXilinx Virtex-5 fifo, different clock for read and write ports.Uses\family typewriterxilinx_fifo.v\family default,\family typewriterxilinx_fifo144.v\family defaultand\family typewriterxilinx_fifo216.v\family default.\end_layout\begin_layout Standard\family typewriterxilinx_fifo_sc.v\family defaultand\family typewriterxilinx_fifo_dc.v\family defaultimplement fifos using FIFO18, FIFO18_36, FIFO36 or FIFO36_72 Virtex-5 primitives.Table\begin_inset CommandInset refLatexCommand refreference "tab:Xilinx-FIFO-address"\end_insetlists available data and address widths.If a\family typewriterxilinx_fifo_sc.v\family defaultor a\family typewriterxilinx_fifo_dc.v\family defaultis instantiated with data and/or address widths different from those inTable\begin_inset CommandInset refLatexCommand refreference "tab:Xilinx-FIFO-address"\end_inset, the actual fifo will be larger and/or wider.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Tabular<lyxtabular version="3" rows="12" columns="4"><features tabularvalignment="middle"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutData bits\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutAddress bits\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO Depth\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutImplementation\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout4\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout13\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout8192\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO36\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" 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topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout4096\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO36\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout9\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout11\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2048\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO18\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout18\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout11\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2048\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO36\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout18\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout10\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1024\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO18\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout36\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout10\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout1024\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO36\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout36\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout9\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout512\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO18\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout72\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout9\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout512\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutFIFO36_72\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout144\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout9\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout512\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout2 * FIFO36_72\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout216\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout9\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout512\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout3 * FIFO36_72\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Xilinx-FIFO-address"\end_insetXilinx FIFO address widths\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout SubsectionMemory mapping\end_layout\begin_layout StandardThe MPEG2 decoder memory mapping is defined in\family typewriterrtl/mpeg2/mem_codes.v\family default.The default memory mapping needs 4 mbyte RAM and is sufficient for SDTV.By defining\family typewriterMP_AT_HL\family defaultan alternative memory mapping can be chosen which requires 16 mbyte RAMand is sufficient for HDTV.\end_layout\begin_layout StandardTranslation of macroblock addresses to memory addresses is implemented in\family typewriterrtl/mpeg2/mem_addr.v\family default.A macroblock address, a signed motion vector (mv_x, mv_y) with halfpixelprecision, and an signed offset (delta_x, delta_y) with pixel precisionare translated to an address in memory.\end_layout\begin_layout StandardThe macroblock address is assumed to iterate over all allowable values:beginning at zero, incrementing by one, until after the final macroblockthe macroblock address is reset to zero.Macroblock address has to be initialized to zero, or an error conditionresults.Macroblock address changes other than incrementing by one, remaining unchangedor resetting to zero also result in an error condition.\end_layout\begin_layout StandardNote the motion vector (mv_x, mv_y) is scaled by a factor two when accessingchrominance as defined in\begin_inset CommandInset citationLatexCommand citeafter "par. 7.6.3.7"key "key-1"\end_inset.The offset (delta_x, delta_y) remains unchanged when accessing chrominanceblocks.\end_layout\begin_layout StandardThe translation of macroblock addresses and motion vectors to memory addressesin\family typewriterrtl/mpeg2/mem_addr.v\family defaulthas to be kept synchronized with the framestore dump task\family typewriterwrite_framestore\family defaultin\family typewriterrtl/sim/mem_ctl.v\family default, else the framestore dumps made during simulation will not accurately representframestore contents.\end_layout\begin_layout StandardNote out-of-range memory accesses are translated to the ADDR_ERR address.If a memory request with address\family typewritermem_req_rd_addr\family defaultequal to ADDR_ERR occurs during simulation, simulation stops with an errormessage.\end_layout\begin_layout StandardThe MPEG2 decoder zeroes out the framestore after system reset or when thewatchdog timer expires.The MPEG2 decoder writes zeroes to all addresses from FRAME_0_Y to VBUF_ENDwhen the\family typewriterrst\family defaultinput pin goes low or when the\family typewriterwatchdog_rst\family defaultpin goes low.\end_layout\begin_layout SubsectionModeline\end_layout\begin_layout StandardThe default modeline is 800x600 progressive @ 60 Hz (SVGA).The\family typewritermodeline.v\family defaultsource contains the modeline parameters, and can be edited to change horizontaland vertical resolution, sync pulse width and position.The default pixel frequency on the ML505 is 38.21 MHz, and is defined in\family typewriterdotclock_synthesizer.v\family default.Note\family typewriterdotclock_synthesizer.v\family defaultsynthesizes two frequencies, dotclock and dotclock90, equal in frequencybut 90 degrees phase shifted.The frequency synthesized is\begin_inset Formula\[f_{out}=f_{osc}.r.\frac{DCM\_ADV\_INST.CLKFX\_MULTIPLY}{DCM\_ADV\_INST.CLKFX\_DIVIDE}\]\end_inset\end_layout\begin_layout Standardwhere\begin_inset Formula $f_{osc}$\end_insetis the 100 MHz user clock frequency\begin_inset Formula\[f_{osc}=100\]\end_insetand\begin_inset Formula\[r=\frac{PLL\_ADV\_INST.CLKFBOUT\_MULT}{PLL\_ADV\_INST.CLKOUT1\_DIVIDE}=0.25\]\end_insetTo change pixel frequency, first calculate the multiplier and divider forthe new frequency.Suppose one wishes to synthesize a frequency of 35 MHz:\end_layout\begin_layout LyX-Codemacpro mpeg2ether # ./mpeg2ether --dot_clock 35\end_layout\begin_layout LyX-Codedotclock ftarget = 35.00 fout = 35.00 MHz\begin_inset Newline newline\end_insetmultiplier: 7 divider: 5\begin_inset Newline newline\end_insethigh frequency mode: 0 ch7301 lowfreq: 1 ch7301 colorbars: 0\end_layout\begin_layout StandardA pixel frequency of 35 MHz requires a multiplier of 7 and a divider of5, with lowfreq asserted.Hence, in\family typewriterdvi/dotclock.v\family default:\end_layout\begin_layout LyX-Codeparameter [7:0]\end_layout\begin_layout LyX-CodeDEFAULT_DIVIDER = 8'd4, // Divider minus one, actually\end_layout\begin_layout LyX-CodeDEFAULT_MULTIPLIER = 8'd6; // Multiplier minus one, actually\end_layout\begin_layout LyX-Code\end_layout\begin_layout LyX-Codeparameter\end_layout\begin_layout LyX-CodeDEFAULT_LOWFREQ = 1'b1\end_layout\begin_layout LyX-Code\end_layout\begin_layout StandardNote the modeline can be configured at any time using the\family typewritermpeg2ether\family defaultutility; it is only when changing the\emph ondefault\emph defaultmodeline that modifying the sources is necessary.The\family typewritermpeg2ether\family defaultutility is explained on page\begin_inset CommandInset refLatexCommand pagerefreference "subsec:mpeg2ether"\end_inset.\end_layout\begin_layout SubsectionInverse Discrete Cosine Transform\end_layout\begin_layout StandardThe IDCT algorithm used is described in\begin_inset CommandInset citationLatexCommand citekey "key-3"\end_inset.A copy of document\begin_inset CommandInset citationLatexCommand citekey "key-3"\end_insetcan be found in the\family typewriterdoc\family defaultdirectory.The IDCT implementation uses 12 18x18 multipliers and two dual-port rams,and can do streaming.Run-length decoding (\family typewriterrld.v\family default), inverse quantizing (\family typewriteriquant.v, zigzag_table.v\family default) and IDCT transform (\family typewriteridct.v\family default) all operate at the same speed of one pixel per clock.The IDCT meets the requirements of the former IEEE-1180.\end_layout\begin_layout SubsectionBilinear chroma upsampling\end_layout\begin_layout StandardThe chrominance components have half the vertical and half the horizontalresolution of the luminance.To obtain equal chrominance and luminance resolution, bilinear chroma upsampling is used.Bilinear chroma upsampling computes chroma pixel values by vertical andhorizontal interpolation.Vertical interpolation implies adding two rows of chroma values with differentweights.The chroma row closest to the luma row gets weight 3/4, while the chromarow farthest from the luma row gets weight 1/4.The document\family typewriterdoc/bilinear.pdf\family defaultshows the weights used.\begin_inset Separator latexpar\end_inset\end_layout\begin_layout StandardBilinear chroma upsampling is implemented in various source files, as describedin Table\begin_inset CommandInset refLatexCommand refreference "tab:Upsampling-source-files"\end_inset.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset Tabular<lyxtabular version="3" rows="5" columns="2"><features tabularvalignment="middle"><column alignment="left" valignment="top"><column alignment="left" valignment="top"><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutSource\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutDescription\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterresample.v\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutUpsampling top-level file\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterresample_addrgen.v\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutGenerates memory addresses of chroma/lumi rows\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterresample_dta.v\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutReads chroma/lumi rows from memory\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterresample_bilinear.v\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain LayoutPerforms bilinear upsampling calculations\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Upsampling-source-files"\end_insetUpsampling source files\end_layout\end_inset\end_layout\begin_layout Plain Layout\end_layout\end_inset\end_layout\begin_layout SectionSimulation\end_layout\begin_layout StandardBehavioral simulation using Icarus Verilog is described.For timing simulation consult your synthesis software.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:Icarus-Verilog-Simulation"\end_insetIcarus Verilog Simulation\end_layout\begin_layout StandardBehavioral simulation of the decoder can be performed using Icarus Verilog.The Icarus Verilog testbench in the\family typewriterbench/iverilog\family defaultdirectory contains the following files:\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritertestbench.v\family defaultTop-level Verilog source; instantiates MPEG2 decoder.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritermem_ctl.v\family defaultSimple memory controller, for simulation only.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterMakefile\family defaultMakefile to create and run the simulation.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewriterwrappers.v\family defaultWrapper for dual-port ram and fifos.Implements synchronous fifos using\family typewriterxfifo_sc.v\family default, and implements asynchronous fifos as OpenCores\family typewritergeneric_fifo_sc_b.v\family default.\end_layout\begin_layout Labeling\labelwidthstring 00.00.0000\family typewritergeneric_dpram.v, generic_fifo_dc.v, generic_fifo_sc_b.v\family defaultOpencores generic fifos.\end_layout\begin_layout StandardCreate the decoder is easy using the accompanying\family typewriterMakefile\family default.First, remove any files left over from a previous simulation:\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/bench/iverilog $ make clean\end_layout\begin_layout LyX-Coderm -f mpeg2 stream.dat testbench.lxt trace framestore_*.ppm tv_out_*.ppm\end_layout\begin_layout StandardNow create the decoder:\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/bench/iverilog $ make\end_layout\begin_layout LyX-Codeiverilog -D__IVERILOG__ -DMODELINE_SIF -I ../../rtl/mpeg2 -o mpeg2\begin_inset Newline newline\end_insettestbench.v mem_ctl.v wrappers.v generic_fifo_dc.v\begin_inset Newline newline\end_insetgeneric_fifo_sc_b.v generic_dpram.v ../../rtl/mpeg2/mpeg2video.v\begin_inset Newline newline\end_inset../../rtl/mpeg2/vbuf.v ../../rtl/mpeg2/getbits.v\begin_inset Newline newline\end_insetxxd -c 1 ../../tools/streams/stream-susi.mpg |\begin_inset Newline newline\end_insetcut -d\backslash-f 2 > stream.dat\end_layout\begin_layout StandardThis executes two commands:\end_layout\begin_layout Itemize\family typewriteriverilog\family defaultto compile the Verilog sources to an executable,\family typewritermpeg2\family default.\end_layout\begin_layout Itemize\family typewriterxxd\family defaultto convert the binary MPEG2 program stream file\family typewriterstream.mpg\family defaultto an ASCII file\family typewriterstream.dat\family default, which the simulator can load.\end_layout\begin_layout StandardWhen compiling the Verilog sources, two Verilog parameters are defined onthe command line:\family typewriter__IVERILOG__\family defaultand\family typewriterMODELINE_SIF\family default.The first Verilog define,\family typewriter__IVERILOG__\family default, is defined only during simulation, and never during synthesis.It is used to enable several run-time checks which only make sense in asimulation environment.The second Verilog define,\family typewriterMODELINE_SIF\family default, chooses one of several pre-defined video output formats from\family typewritermodeline.v\family default.\end_layout\begin_layout StandardFinally, run the newly created executable\family typewritermpeg2:\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/bench/iverilog $ make test\end_layout\begin_layout LyX-CodeIVERILOG_DUMPER=lxt ./mpeg2\end_layout\begin_layout LyX-CodeLXT info: dumpfile testbench.lxt opened for output.\end_layout\begin_layout LyX-Code$readmemh(stream.dat): Not enough words in the read file for\begin_inset Newline newline\end_insetrequested range.\end_layout\begin_layout LyX-Codetestbench.mem_ctl.write_framestore dumping framestore to\begin_inset Newline newline\end_insetframestore_000.ppm @ 0.02 ms\end_layout\begin_layout LyX-Codetestbench.mem_ctl.write_framestore dumping framestore to\begin_inset Newline newline\end_insetframestore_001.ppm @ 0.02 ms\end_layout\begin_layout LyX-Codetestbench.mpeg2.motcomp macroblock_address: 0\end_layout\begin_layout LyX-Codetestbench.mpeg2.motcomp macroblock_address: 1\end_layout\begin_layout LyX-Codetestbench.mpeg2.motcomp macroblock_address: 2\end_layout\begin_layout LyX-Codetestbench.mpeg2.motcomp macroblock_address: 3\end_layout\begin_layout StandardDuring simulation, the environment variable\family typewriterIVERILOG_DUMPER=lxt\family defaultis set.This instructs the simulator to produce a dumpfile in the more compact\family typewriterlxt\family defaultformat, instead of the default\family typewritervcd\family defaultformat.\end_layout\begin_layout StandardBy default, simulator output includes the macroblock address.This allows easy monitoring of decoder progress\family typewriter.\end_layout\begin_layout StandardEach Verilog source file contains a\family typewriterdefine DEBUG\family defaultstatement, which can be uncommented or commented to switch trace outputfor that particular source file on or off.\end_layout\begin_layout StandardDuring simulation, two kinds of graphics files are written: framestore dumps\family typewriterframestore_*.ppm\family defaultand video captures\family typewritertv_out_*.ppm\family default.The framestore is where the decoder stores already decoded images.These are Portable Pixmap graphics files in ASCII format.Figure\begin_inset CommandInset refLatexCommand refreference "fig:susi-framestore-dump"\end_insetshows a sample framestore dump.\end_layout\begin_layout StandardThe framestore consists of four frames and the on-screen display (OSD).The first two frames contain I and P pictures, while the last two framescontain B-pictures.Each frame consists of y (luminance), u and v (chrominance) information,with u and v having half the horizontal and half the vertical resolutionof y.In the framestore dump, uninitialized memory is displayed in green.Looking at figure\begin_inset CommandInset refLatexCommand refreference "fig:susi-framestore-dump"\end_inset, one can see that the first three frames of the framestore have alreadybeen written; the decoder is halfway through the fourth frame.The On-Screen Display, at the bottom of the framestore dump, has not beeninitialized yet.\end_layout\begin_layout StandardDuring simulation, by default, the framestore is dumped whenever a new framebegins; and every 200 macroblocks.As a framestore dump is a graphics file in ASCII format, one can also lookat the file using standard text file utilities.These are the first 12 lines of a sample framestore dump:\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/bench/iverilog\family typewriter$ head -12 framestore_0001.ppm\end_layout\begin_layout LyX-Code\family typewriterP3\end_layout\begin_layout LyX-Code\family typewriter# mpeg2 framestore dump @ 11.81 ms\end_layout\begin_layout LyX-Code\family typewriter# frame number 2\end_layout\begin_layout LyX-Code\family typewriter# horizontal_size 352\end_layout\begin_layout LyX-Code\family typewriter# vertical_size 288\end_layout\begin_layout LyX-Code\family typewriter# display_horizontal_size 0\end_layout\begin_layout LyX-Code\family typewriter# display_vertical_size 0\end_layout\begin_layout LyX-Code\family typewriter# mb_width 22\end_layout\begin_layout LyX-Code\family typewriter# mb_height 18\end_layout\begin_layout LyX-Code\family typewriter# picture_structure frame picture\end_layout\begin_layout LyX-Code\family typewriter# chroma_format 420\end_layout\begin_layout LyX-Code\family typewriter352 2618 255\end_layout\begin_layout LyX-Code\family typewriter255 255 255 255 255 255 255 255 255 255 255 255\begin_inset Newline newline\end_inset255 255 255 255 255 255 255 255 255 255 255 255\end_layout\begin_layout StandardThe header of the framestore dump contains information about decoder statusat the moment of the dump.\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\align center\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Graphicsfilename framestore_001.pslyxscale 20height 80theight%\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:susi-framestore-dump"\end_insetFramestore dump\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout StandardFigure\begin_inset CommandInset refLatexCommand refreference "fig:susi-video-output"\end_insetshows video capture file\family typewritertv_out_0000.ppm.\family defaultHorizontal sync is displayed as a vertical black stripe, to the right ofthe image.Vertical sync is displayed as a horizontal black stripe, below the imagearea.Blanking is displayed in a dark grey.The position of picture, horizontal sync and vertical sync in figure\begin_inset CommandInset refLatexCommand refreference "fig:susi-video-output"\end_insetis as defined in figure\begin_inset CommandInset refLatexCommand refreference "fig:Progressive-Video"\end_inset.As with the framestore dumps, one can look at\family typewritertv_out_0000.ppm\family defaultusing standard text utilities.\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/bench/iverilog\family typewriter$ head -10 tv_out_0000.ppm\end_layout\begin_layout LyX-Code\family typewriterP3\end_layout\begin_layout LyX-Code\family typewriter# picture 1 @ 10.73 ms\end_layout\begin_layout LyX-Code\family typewriter# horizontal resolution 352 sync_start 381 sync_end 388 length 458\end_layout\begin_layout LyX-Code\family typewriter# vertical resolution 288 sync_start 295 sync_end 298 length 315\end_layout\begin_layout LyX-Code\family typewriter# interlaced 0 halfline 175\end_layout\begin_layout LyX-Code\family typewriter459 316 255\end_layout\begin_layout LyX-Code\family typewriter0 0 0\end_layout\begin_layout LyX-Code\family typewriter0 77 0\end_layout\begin_layout LyX-Code\family typewriter3 0 3\end_layout\begin_layout LyX-Code\family typewriter2 0 2\end_layout\begin_layout StandardThe header of the video capture file contains information about the videomodeline at the moment of video capture.\begin_inset Float figurewide falsesideways falsestatus open\begin_layout Plain Layout\begin_inset ERTstatus open\begin_layout Plain Layout\backslashcentering\end_layout\end_inset\begin_inset Graphicsfilename tv_out_0.pswidth 60line%\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "fig:susi-video-output"\end_insetVideo output capture\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout StandardTo end the simulation, go to the window where iverilog is running and type\family typewriterctrl-c finish\family default.The simulator will finish writing\family typewritertrace\family defaultand\family typewritertestbench.lxt\family defaultfiles, and return control to the command prompt.\end_layout\begin_layout StandardThe binary file\family typewritertestbench.lxt\family defaultis a log of all wire and register changes which occurred during simulation.\family typewritertestbench.lxt\family defaultcan be displayed using vcd viewers such as\family typewritergtkwave\family default.\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/bench/iverilog\family typewriter$ gtkwave testbench.lxt &\end_layout\begin_layout StandardOnce\family typewritertestbench.lxt\family defaultfile has been loaded in\family typewritergtkwave\family default, internal decoder wires and registers can be displayed as waveforms.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:Conformance-Tests"\end_insetConformance Tests\end_layout\begin_layout StandardThe\family typewriterbench/conformance\family defaultdirectory contains a testbench for the ISO/IEC 13818-4 MPEG2 conformancetests.The testbench assumes the ISO/IEC 13818-4 conformance test bitstreams areavailable on your system.The ISO/IEC 13818-4 MPEG2 Conformance test bitstreams for Main Profile@ Main Level can be downloaded from the ISO web site using the\family typewritertools/streams/retrieve\family defaultscript.\end_layout\begin_layout StandardTyping\family typewritermake clean test\family defaultin the\family typewriterbench/conformance\family defaultdirectory simulates all MP@ML conformance test bitstreams.Table\begin_inset CommandInset refLatexCommand refreference "tab:Conformance-Test-Suite"\end_insetsummarizes test results.\end_layout\begin_layout StandardWhen running the compatibility tests, note the decoder is not MPEG1-compatible,and does not decode MPEG1 streams.The MPEG2 decoder decodes MPEG2 4:2:0 program streams only.\begin_inset Float tablewide falsesideways falsestatus open\begin_layout Plain Layout\begin_inset Tabular<lyxtabular version="3" rows="43" columns="3"><features tabularvalignment="middle"><column alignment="left" valignment="top"><column alignment="center" valignment="top"><column alignment="center" valignment="top"><row><cell alignment="center" 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Layout\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewriterhhi/hhi_burst_long\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family roman\series medium\shape up\size normal\emph off\bar no\noun off\color noneMP@ML\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell></row><row><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family typewritertcela/tcela-10-killer\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\family roman\series medium\shape up\size normal\emph off\bar no\noun off\color noneMP@ML\end_layout\end_inset</cell><cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">\begin_inset Text\begin_layout Plain Layout\end_layout\end_inset</cell></row></lyxtabular>\end_inset\end_layout\begin_layout Plain Layout\begin_inset Caption Standard\begin_layout Plain Layout\begin_inset CommandInset labelLatexCommand labelname "tab:Conformance-Test-Suite"\end_insetConformance Test Suite\end_layout\end_inset\end_layout\end_inset\end_layout\begin_layout Section\begin_inset CommandInset labelLatexCommand labelname "sec:Tools"\end_insetTools\end_layout\begin_layout StandardThe\family typewritertools\family defaultdirectory contains various utilities and tools used during decoder developmentand test.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:Logicport-Logic-Analyzer"\end_insetLogic Analyzer\end_layout\begin_layout StandardOn the Xilinx ML505, the MPEG2 decoder testpoint has been broken out tothe Xilinx Generic Interface (XGI) .The test point selection can be done using the GPIO DIP switches.If the ML505 is held so the LCD can be read, the GPIO DIP switches areat the bottom right of the board.GPIO DIP switches are numbered 1 to 8, from left to right.\end_layout\begin_layout StandardIf GPIO DIP switch 3 is off, test point selection is made by writing toregister 15 decimal, REG_WR_TESTPOINT.If GPIO DIP switch 3 is on, test point selection is made by dip switches5 to 8.GPIO DIP switch 5 is MSB, GPIO DIP switch 8 is LSB.\end_layout\begin_layout StandardVerify the probing has been enabled in\family typewriterprobe.v\family default.Note that, as one adds test points, routing and timing closure becomesmore and more difficult.Only define those test points you need.\end_layout\begin_layout StandardThe Intronix Logicport is a small USB-based logic analyzer.It has 34 channels, two of which can be used as clock inputs, and doesstate analysis at up to 200 MHz.The MPEG2 decoder on the ML505 runs at 75 MHz, with a typical dot clockof 27 MHz, well within the capabilities of the Logicport logic analyzer.Probing the memory controller at 200 MHz, however, is borderline.To be on the safe side, when probing the memory controller with the Logicport,lower memory clock to 125 MHz .\end_layout\begin_layout StandardA small two-layer adapter board has been designed to connect the IntronixLogicport to the Xilinx ML505.Board layout can be downloaded from\begin_inset Flex URLstatus collapsed\begin_layout Plain Layouthttp://www.kdvelectronics.eu/probe_adapter/probe_adapter.html\end_layout\end_inset.\end_layout\begin_layout StandardThe\family typewritertools/logicport\family defaultdirectory contains Logicport configuration files for the test points definedin\family typewriterprobe.v\family default.Note configuration files can be read and waveforms displayed by Logicportsoftware even if no analyzer is present.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:FSM-Graphs"\end_insetFinite State Machine Graphs\end_layout\begin_layout StandardThe MPEG2 decoder uses Finite State Machines throughout; no embedded processorsor microcontrollers are used.Verifying the correctness of the Finite State Machines is important.Finite state machine transition graphs are created from Verilog sourcefiles as a means of visually inspecting and verifying source correctness.The\family typewritermkfsmgraph\family defaultPerl script in\family typewritertools/fsmgraph\family defaultassumes the comment\family typewriter/* next state logic */\family defaultmarks the beginning of a\family typewritercase\family defaultstatement in an\family typewriteralways\family defaultblock, used to select the next state, and that all states begin with STATE_:\end_layout\begin_layout LyX-Code/* next state logic */\end_layout\begin_layout LyX-Codealways @*\end_layout\begin_layout LyX-Codecase (state)\end_layout\begin_layout LyX-CodeSTATE_INIT: if (first_pixel_read) next = STATE_WAIT;\end_layout\begin_layout LyX-Codeelse next = STATE_INIT;\end_layout\begin_layout LyX-Code...\end_layout\begin_layout LyX-Codedefault next = STATE_INIT\end_layout\begin_layout LyX-Codeendcase\end_layout\begin_layout LyX-Code/* state */\end_layout\begin_layout LyX-Codealways @(posedge clk)\end_layout\begin_layout LyX-Codeif(~rst) state <= STATE_INIT;\end_layout\begin_layout LyX-Codeelse state <= next;\end_layout\begin_layout StandardThe\family typewritermkfsmgraph\family defaulttool parses the Verilog source files using the following algorithm:\end_layout\begin_layout Itemizeread the Verilog file until the comment\family typewriter/* next state logic */\family defaultis found\end_layout\begin_layout Itemizetake the first\family typewriteralways\family defaultblock after the\family typewriter/* next state logic */\family defaultcomment\end_layout\begin_layout Itemizeany word beginning with\family typewriterSTATE_\family defaultis assumed to represent a FSM state.\end_layout\begin_layout Itemizeif the character following the FSM state is a colon (:) the state is a graphnode.\end_layout\begin_layout Itemizeif the character following the FSM state is a semicolon (;) the state isthe end point of a state transition.\end_layout\begin_layout Itemizeif the character following the FSM state is neither a colon (:) nor a semicolon(;) the state is not added to the graph.\end_layout\begin_layout StandardThe resulting graph is written to standard output in gml format.Graph layout software uDrawGraph from the University of Bremen, Germany,is then used to produce a visually appealing graph.\end_layout\begin_layout StandardNo attempt has been made to write a script capable of parsing arbitraryVerilog sources.The Verilog sources have been written so the script can parse them.\end_layout\begin_layout StandardThe graph of the variable length-decoding FSM\family typewritervld.v\family defaulthas been simplified further by removing all transitions to STATE_NEXT_START_CODE and STATE_ERROR.Nodes which transition to STATE_NEXT_START_CODE are drawn with double border.Removing transitions to STATE_NEXT_START_CODE and STATE_ERROR producesa graph with much less visual clutter.A large format version of the FMS graph of\family typewritervld.v\family defaultcan be found in\family typewriterdoc/vld-poster.pdf\family default.It is suggested to become familiar with the graph before significantlymodifying\family typewritervld.v\family default.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:IEEE-1180-IDCT"\end_insetIEEE-1180 IDCT Accuracy Test\end_layout\begin_layout Standard\family typewriteridct.v\family defaulthas been tested to comply with the former IEEE-1180, the actual ISO/IEC23002-1\begin_inset CommandInset citationLatexCommand citekey "key-5"\end_inset.The testbench can be found in the\family typewritertools/ieee1180\family defaultdirectory.Test results can be found in the file\family typewriterieee-1180-results\family default.Test results indicate the idct implementation is IEEE-1180 compliant.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:mpeg2decode"\end_insetReference software decoder\end_layout\begin_layout StandardThe directory\family typewritertools/mpeg2dec\family defaultcontains the MPEG2 reference decoder, modified to provide extensive loggingand to regularly write the framebuffers to file.A sample run could be:\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/tools $ mkdir run\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/tools $ cd run\end_layout\begin_layout LyX-Codekoen@macpro ~/xilinx/mpeg2/tools/run $ ../mpeg2dec/mpeg2decode\begin_inset Newline newline\end_inset-r -v9 -t -o0 'dump_%d_out_%c' -b ../streams/tcela-17.mpg > log\end_layout\begin_layout LyX-Codesaving dump_0_out_f.y.ppm\end_layout\begin_layout LyX-Codesaving dump_0_out_f.u.ppm\end_layout\begin_layout LyX-Codesaving dump_0_out_f.v.ppm\end_layout\begin_layout LyX-Codesaving dump_0_forward_ref_frm.y.ppm\end_layout\begin_layout LyX-Codesaving dump_0_forward_ref_frm.u.ppm\end_layout\begin_layout LyX-Codesaving dump_0_forward_ref_frm.v.ppm\end_layout\begin_layout LyX-Codesaving dump_0_backward_ref_frm.y.ppm\end_layout\begin_layout LyX-Codesaving dump_0_backward_ref_frm.u.ppm\end_layout\begin_layout LyX-Codesaving dump_0_backward_ref_frm.v.ppm\end_layout\begin_layout LyX-Codesaving dump_0_auxframe.y.ppm\end_layout\begin_layout LyX-Codesaving dump_0_auxframe.u.ppm\end_layout\begin_layout LyX-Codesaving dump_0_auxframe.v.ppm\end_layout\begin_layout LyX-Codesaving dump_1_out_f.y.ppm\end_layout\begin_layout LyX-Codesaving dump_1_out_f.u.ppm\end_layout\begin_layout LyX-Code...\end_layout\begin_layout StandardThe\family typewriterlog\family defaultfile contains detailed information about the execution of the MPEG2 decodingalgorithm, while the\family typewriter.ppm\family defaultfiles contain framestore dumps, using separate graphics files for eachy, u and v component.\end_layout\begin_layout Subsection\begin_inset CommandInset labelLatexCommand labelname "subsec:MPEG2-Test-Streams"\end_insetMPEG2 Test Streams\end_layout\begin_layout StandardThe\family typewritertools/streams\family defaultdirectory contains some sample MPEG2 program streams, useful during testing.The\family typewriterretrieve\family defaultscript in the\family typewritertools/streams\family defaultdirectory can be used to download the ISO/IEC 13818-4 conformance testbitstreams from the ISO web site\begin_inset Footstatus open\begin_layout Plain LayoutISO/IEC 13818-4 test bitstreams,\begin_inset Flex URLstatus collapsed\begin_layout Plain Layouthttp://standards.iso.org/ittf/PubliclyAvailableStandards/ISO_IEC_13818-4_2004_Conformance_Testing/Video/bitstreams/main-profile/\end_layout\end_inset\end_layout\end_inset.\end_layout\begin_layout Bibliography\begin_inset CommandInset bibitemLatexCommand bibitemlabel "1"key "key-1"\end_insetITU-T Recommendation H.262\begin_inset Quotes eld\end_insetInformation technology - Generic coding of moving pictures and associatedaudio information: Video\begin_inset Quotes erd\end_inset, 2000.Also published as ISO/IEC International Standard 13818-2.\end_layout\begin_layout Bibliography\begin_inset CommandInset bibitemLatexCommand bibitemlabel "2"key "key-5"\end_insetISO/IEC International Standard 23002-1\begin_inset Quotes eld\end_insetInformation technology - MPEG video technologies - Part 1: Accuracy requirementsfor implementation of integer-output 8x8 inverse discrete cosine transform\begin_inset Quotes erd\end_inset, 2006.\end_layout\begin_layout Bibliography\begin_inset CommandInset bibitemLatexCommand bibitemlabel "3"key "key-2"\end_inset\begin_inset Quotes eld\end_insetArchitecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder", Jui-HuaLi and Nam Ling, IEEE Transactions on Circuits and Systems for Video Technology, Vol.9, No.5, August 1999, p.727-736.\end_layout\begin_layout Bibliography\begin_inset CommandInset bibitemLatexCommand bibitemlabel "4"key "key-3"\end_inset\begin_inset Quotes eld\end_insetSystematic approach of Fixed Point 8x8 IDCT and DCT Design and Implementation",Ci-Xun Zhang , Jing Wang , Lu Yu, Institute of Information and CommunicationEngineering, Zhejiang University, Hangzhou, China, 310027.\end_layout\begin_layout Bibliography\begin_inset CommandInset bibitemLatexCommand bibitemlabel "5"key "key-4"\end_inset\begin_inset Quotes eld\end_insetVirtex-5 FPGA User Guide\begin_inset Quotes erd\end_inset, Xilinx UG190 (v3.2), December 11, 2007.\end_layout\begin_layout Bibliography\begin_inset CommandInset bibitemLatexCommand bibitemlabel "6"key "key-7"\end_inset\begin_inset Quotes eld\end_insetML505/506 MIG Design Creation Using ISE 9.2i SP3, MIG 2.0 and ChipScope Pro9.2i\begin_inset Quotes erd\end_inset, Xilinx, December 2007.\end_layout\end_body\end_document
