Subversion Repositories mpmc8

`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
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// 3. Neither the name of the copyright holder nor the names of its
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// ============================================================================
//
import mpmc8_pkg::*;

module mpmc8_strm_read_cache(rst, wclk, wr, wadr, wdat, inv,
        rclk, radr, rdat, hit
);
input rst;
input wclk;
input wr;
input [31:0] wadr;
input [127:0] wdat;
input inv;
input rclk;
input [31:0] radr;
output reg [127:0] rdat;
output reg hit;

(* ram_style="distributed" *)
reg [127:0] lines [0:31];
(* ram_style="distributed" *)
reg [27:0] tags [0:31];
(* ram_style="distributed" *)
reg [31:0] vbit;
reg [31:0] radrr;
reg [27:0] tago;
reg vbito;

always_ff @(posedge rclk)
        radrr <= radr;
always_ff @(posedge wclk)
        if (wr) lines[wadr[8:4]] <= wdat;
always_ff @(posedge rclk)
        rdat <= lines[radrr[8:4]];
always_ff @(posedge rclk)
        tago <= tags[radrr[8:4]];
always_ff @(posedge rclk)
        vbito <= vbit[radrr[8:4]];
always_ff @(posedge wclk)
        if (wr) tags[wadr[8:4]] <= wadr[31:4];
always_ff @(posedge wclk)
if (rst)
        vbit <= 'b0;
else begin
        if (wr)
                vbit[wadr[8:4]] <= 1'b1;
        else if (inv)
                vbit[wadr[8:4]] <= 1'b0;
end
always_comb
        hit = (tago==radrr[31:4]) && (vbito==1'b1);

endmodule