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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_resv_bit.sv] - Rev 11
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`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// BSD 3-Clause License
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// modification, are permitted provided that the following conditions are met:
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// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
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// ============================================================================
//
import mpmc10_pkg::*;
// Reservation status bit
module mpmc10_resv_bit(clk, state, wch, we, cr, adr, resv_ch, resv_adr, rb);
input clk;
input mpmc10_state_t state;
input we;
input cr;
input [3:0] wch;
input [31:0] adr;
input [3:0] resv_ch [0:mpmc10_pkg::NAR-1];
input [31:0] resv_adr [0:mpmc10_pkg::NAR-1];
output reg rb;
integer n5;
always_ff @(posedge clk)
if (state==IDLE) begin
if (we) begin
if (cr) begin
rb <= 1'b0;
for (n5 = 0; n5 < mpmc10_pkg::NAR; n5 = n5 + 1)
if ((resv_ch[n5]==wch) && (resv_adr[n5][31:5]==adr[31:5]))
rb <= 1'b1;
end
end
end
endmodule