Subversion Repositories mpmc8

`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// BSD 3-Clause License
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// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
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//    this list of conditions and the following disclaimer in the documentation
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// ============================================================================
//
import mpmc8_pkg::*;

module mpmc8_addr_select(rst, clk, state, ch,
        we0, we1, we2, we3, we4, we5, we6, we7,
        adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7,
        adr);
parameter S0 = 3'd7;
parameter S1 = 3'd1;
parameter S2 = 3'd0;
parameter S3 = 3'd0;
parameter S4 = 3'd0;
parameter S5 = 3'd3;
parameter S6 = 3'd0;
parameter S7 = 3'd3;
input rst;
input clk;
input [3:0] state;
input [3:0] ch;
input we0;
input we1;
input we2;
input we3;
input we4;
input we5;
input we6;
input we7;
input [31:0] adr0;
input [31:0] adr1;
input [31:0] adr2;
input [31:0] adr3;
input [31:0] adr4;
input [31:0] adr5;
input [31:0] adr6;
input [31:0] adr7;
output reg [31:0] adr;

// Select the address input
reg [31:0] adrx;
always_ff @(posedge clk)
if (state==IDLE) begin
        case(ch)
        3'd0:   if (we0)
                                adrx <= {adr0[AMSB:4],4'h0};
                        else
                                case(S0)
                                3'd0:   adrx <= {adr0[AMSB:4],4'h0};
                                3'd1:   adrx <= {adr0[AMSB:5],5'h0};
                                3'd3:   adrx <= {adr0[AMSB:6],6'h0};
                                3'd7:   adrx <= {adr0[AMSB:7],7'h0};
                                default:        adrx <= {adr0[AMSB:7],7'h0};
                                endcase
        3'd1:   if (we1)
                                adrx <= {adr1[AMSB:4],4'h0};
                        else
                                case(S1)
                                3'd0:   adrx <= {adr1[AMSB:4],4'h0};
                                3'd1:   adrx <= {adr1[AMSB:5],5'h0};
                                3'd3:   adrx <= {adr1[AMSB:6],6'h0};
                                3'd7:   adrx <= {adr1[AMSB:7],7'h0};
                                default: adrx <= {adr1[AMSB:5],5'h0};
                                endcase
        3'd2:   if (we2)
                                        adrx <= {adr2[AMSB:4],4'h0};
                                else
                                        case(S2)
                                        3'd0:   adrx <= {adr2[AMSB:4],4'h0};
                                        3'd1:   adrx <= {adr2[AMSB:5],5'h0};
                                        3'd3:   adrx <= {adr2[AMSB:6],6'h0};
                                        3'd7:   adrx <= {adr2[AMSB:7],7'h0};
                                        default: adrx <= {adr2[AMSB:4],4'h0};
                                        endcase
        3'd3:   if (we3)
                                        adrx <= {adr3[AMSB:4],4'h0};
                                else
                                        case(S3)
                                        3'd0:   adrx <= {adr3[AMSB:4],4'h0};
                                        3'd1:   adrx <= {adr3[AMSB:5],5'h0};
                                        3'd3:   adrx <= {adr3[AMSB:6],6'h0};
                                        3'd7:   adrx <= {adr3[AMSB:7],7'h0};
                                        default: adrx <= {adr3[AMSB:4],4'h0};
                                        endcase
        3'd4:   if (we4)
                                        adrx <= {adr4[AMSB:4],4'h0};
                                else
                                        case(S4)
                                        3'd0:   adrx <= {adr4[AMSB:4],4'h0};
                                        3'd1:   adrx <= {adr4[AMSB:5],5'h0};
                                        3'd3:   adrx <= {adr4[AMSB:6],6'h0};
                                        3'd7:   adrx <= {adr4[AMSB:7],7'h0};
                                        default: adrx <= {adr4[AMSB:4],4'h0};
                                        endcase
        3'd5:   if (we5)
                                        adrx <= {adr5[AMSB:6],6'h0};
                                else
                                        case(S5)
                                        3'd0:   adrx <= {adr5[AMSB:4],4'h0};
                                        3'd1:   adrx <= {adr5[AMSB:5],5'h0};
                                        3'd3:   adrx <= {adr5[AMSB:6],6'h0};
                                        3'd7:   adrx <= {adr5[AMSB:7],7'h0};
                                        default: adrx <= {adr5[AMSB:6],6'h0};
                                        endcase
        3'd6:   if (we6)
                                        adrx <= {adr6[AMSB:4],4'h0};
                                else
                                        case(S6)
                                        3'd0:   adrx <= {adr6[AMSB:4],4'h0};
                                        3'd1:   adrx <= {adr6[AMSB:5],5'h0};
                                        3'd3:   adrx <= {adr6[AMSB:6],6'h0};
                                        3'd7:   adrx <= {adr6[AMSB:7],7'h0};
                                        default: adrx <= {adr6[AMSB:4],4'h0};
                                        endcase
        3'd7:   if (we7) 
                                        adrx <= {adr7[AMSB:4],4'h0};
                                else
                                        case(S7)
                                        3'd0:   adrx <= {adr7[AMSB:4],4'h0};
                                        3'd1:   adrx <= {adr7[AMSB:5],5'h0};
                                        3'd3:   adrx <= {adr7[AMSB:6],6'h0};
                                        3'd7:   adrx <= {adr7[AMSB:7],7'h0};
                                        default: adrx <= {adr7[AMSB:6],6'h0};
                                        endcase
        default:        adrx <= 29'h1FFFFFF0;
        endcase
end
always_ff @(posedge clk)
if (rst)
        adr <= 32'h1FFFFFF0;
else if (state==PRESET1)
        adr <= adrx;

endmodule