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[/] [mpmc8/] [trunk/] [rtl/] [mpmc8_sync.sv] - Rev 4
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`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
//
import mpmc8_pkg::*;
module mpmc8_sync(clk, cs_i, we_i, sel_i, adr_i, dati_i, sr_i, cr_i,
cs_o, we_o, sel_o, adr_o, dati_o, sr_o, cr_o
);
parameter W=128;
input clk;
input cs_i;
input we_i;
input [W/8-1:0] sel_i;
input [31:0] adr_i;
input [W-1:0] dati_i;
input sr_i;
input cr_i;
output reg cs_o;
output reg we_o;
output reg [W/8-1:0] sel_o;
output reg [31:0] adr_o;
output reg [W-1:0] dati_o;
output reg sr_o;
output reg cr_o;
always_ff @(posedge clk)
begin
cs_o <= cs_i;
we_o <= we_i;
sel_o <= sel_i;
adr_o <= adr_i;
dati_o <= dati_i;
sr_o <= sr_i;
cr_o <= cr_i;
end
endmodule
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