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# PlanAhead Generated physical constraints 
NET "clock" LOC = C9;
NET "reset" LOC = H13;

# PlanAhead Generated IO constraints 
NET "clock" IOSTANDARD = LVCMOS33;
NET "reset" IOSTANDARD = LVTTL;

# PlanAhead Generated IO constraints 
NET "txd_line" LOC = M14;
NET "txd_line" IOSTANDARD = LVTTL;
NET "txd_line" DRIVE = 8;
NET "rxd_line" LOC = R7;
NET "rxd_line" IOSTANDARD = LVTTL;
#NET "debug_txd_line" LOC = M13;
#NET "debug_txd_line" IOSTANDARD = LVTTL;
#NET "debug_txd_line" DRIVE = 8;
#NET "debug_rxd_line" LOC = U8;
#NET "debug_rxd_line" IOSTANDARD = LVTTL;

#Created by Constraints Editor (xc3s500e-fg320-4) - 2010/05/30
NET "clock" TNM_NET = "clock";
TIMESPEC TS_clock = PERIOD "clock" 20 ns HIGH 50 %;

NET "reset" PULLDOWN;

# ==== LED output ===
NET "leds[7]" IOSTANDARD = LVTTL;
NET "leds[7]" SLEW = SLOW;
NET "leds[7]" DRIVE = 8;
NET "leds[7]" LOC = F9;
NET "leds[6]" IOSTANDARD = LVTTL;
NET "leds[6]" SLEW = SLOW;
NET "leds[6]" DRIVE = 8;
NET "leds[6]" LOC = E9;
NET "leds[5]" IOSTANDARD = LVTTL;
NET "leds[5]" SLEW = SLOW;
NET "leds[5]" DRIVE = 8;
NET "leds[5]" LOC = D11;
NET "leds[4]" IOSTANDARD = LVTTL;
NET "leds[4]" SLEW = SLOW;
NET "leds[4]" DRIVE = 8;
NET "leds[4]" LOC = C11;
NET "leds[3]" IOSTANDARD = LVTTL;
NET "leds[3]" SLEW = SLOW;
NET "leds[3]" DRIVE = 8;
NET "leds[3]" LOC = F11;
NET "leds[2]" IOSTANDARD = LVTTL;
NET "leds[2]" SLEW = SLOW;
NET "leds[2]" DRIVE = 8;
NET "leds[2]" LOC = E11;
NET "leds[1]" IOSTANDARD = LVTTL;
NET "leds[1]" SLEW = SLOW;
NET "leds[1]" DRIVE = 8;
NET "leds[1]" LOC = E12;
NET "leds[0]" IOSTANDARD = LVTTL;
NET "leds[0]" SLEW = SLOW;
NET "leds[0]" DRIVE = 8;
NET "leds[0]" LOC = F12;

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# PlanAhead Generated physical constraints