URL
https://opencores.org/ocsvn/myblaze/myblaze/trunk
Subversion Repositories myblaze
[/] [myblaze/] [trunk/] [system/] [uart_test_top/] [SysTop.syr] - Rev 6
Compare with Previous | Blame | View Log
Release 10.1.03 - xst K.39 (lin64)Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.-->Parameter TMPDIR set to /home/daniel/Sources/myblaze/system/uart_test_top/xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.05 secs-->Parameter xsthdpdir set to /home/daniel/Sources/myblaze/system/uart_test_top/xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.05 secs-->Reading design: SysTop.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Compilation3) Design Hierarchy Analysis4) HDL Analysis5) HDL Synthesis5.1) HDL Synthesis Report6) Advanced HDL Synthesis6.1) Advanced HDL Synthesis Report7) Low Level Synthesis8) Partition Report9) Final Report9.1) Device utilization summary9.2) Partition Resource Summary9.3) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "SysTop.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "SysTop"Output Format : NGCTarget Device : xc3s500e-4-fg320---- Source OptionsTop Module Name : SysTopAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YESResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 24Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : autoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Library Search Order : SysTop.lsoKeep Hierarchy : NONetlist Hierarchy : as_optimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "../../rtl/SysTop.v" in library workModule <SysTop> compiledNo errors in compilationAnalysis of file <"SysTop.prj"> succeeded.=========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for module <SysTop> in library <work>.=========================================================================* HDL Analysis *=========================================================================Analyzing top module <SysTop>.INFO:Xst:2546 - "../../rtl/SysTop.v" line 667: reading initialization file "rom0.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 680: reading initialization file "rom1.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 693: reading initialization file "rom2.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 706: reading initialization file "rom3.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 732: reading initialization file "rom0.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 745: reading initialization file "rom1.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 758: reading initialization file "rom2.vmem".INFO:Xst:2546 - "../../rtl/SysTop.v" line 771: reading initialization file "rom3.vmem".INFO:Xst:1433 - Contents of array <imem_bank_0_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_0_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_1_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_1_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_2_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_2_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_3_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <imem_bank_3_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_0_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_0_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_1_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_1_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_2_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_2_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_3_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.INFO:Xst:1433 - Contents of array <dmem_bank_3_ram> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.Calling function <MYHDL24_align_mem_load>.Calling function <MYHDL25_sign_extend16>.Calling function <MYHDL30_select_register_data>.Calling function <MYHDL29_forward_condition>.Calling function <MYHDL32_select_register_data>.Calling function <MYHDL31_forward_condition>.Calling function <MYHDL34_select_register_data>.Calling function <MYHDL33_forward_condition>.Calling function <MYHDL35_align_mem_load>.Calling function <MYHDL36_forward_condition>.Calling function <MYHDL37_forward_condition>.Calling function <MYHDL38_forward_condition>.Calling function <MYHDL39_forward_condition>.Calling function <MYHDL40_forward_condition>.Calling function <MYHDL41_align_mem_store>.Calling function <MYHDL42_forward_condition>.Calling function <MYHDL43_align_mem_store>.Calling function <MYHDL44_align_mem_store>.Calling function <MYHDL45_add>.Calling function <MYHDL49_sign_extend8>.Calling function <MYHDL55_sign_extend16>.Calling function <MYHDL63_decode_mem_store>.Module <SysTop> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...INFO:Xst:2679 - Register <led_low> in unit <SysTop> has a constant value of 00000000000000000000000000000001 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <imem_data_out> in unit <SysTop> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <imem_sel_out> in unit <SysTop> has a constant value of 0000 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <read_en2> in unit <SysTop> has a constant value of 0 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <uart2_tx_is_busy> in unit <SysTop> has a constant value of 0 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <uart_txd2> in unit <SysTop> has a constant value of 1 during circuit operation. The register is replaced by logic.Synthesizing Unit <SysTop>.Related source file is "../../rtl/SysTop.v".WARNING:Xst:646 - Signal <tx_data2<31:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <tx_data<31:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <tx_busy2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_error2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_error> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_data2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_avail2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <rx_avail> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <led_reg<31:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <led_low> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <imem_addr_out<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_MEMU_COMB/alu_result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_FTCH_COMB/program_counter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/zero> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/xor_rslt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/transfer_size> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/sel_dat_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/sel_dat_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/sel_dat_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/result_add> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/r_reg_write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/r_reg_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/r_flush_ex> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/r_carry> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/r_alu_result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/program_counter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/or_rslt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/msb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/mem_write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/mem_result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/mem_read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/flush_id> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/dat_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/dat_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/dat_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/cmp_cond> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/carry> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/branch> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/and_rslt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/alu_src_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_EXEU_COMB/alu_src_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/transfer_size> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/reg_write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/reg_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/reg_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_reg_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_program_counter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_mem_read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_instruction> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_immediate_high> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_hazard> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/r_has_imm_high> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/program_counter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/opgroup> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/operation> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/opcode> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/mem_write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/mem_result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/instruction> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/immediate_low> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/immediate> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/has_imm> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/delay> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/carry_keep> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/carry> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/branch_cond> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/alu_src_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/alu_src_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <SYSTOP_CORE_DECO_COMB/alu_op> is assigned but never used. This unconnected signal will be trimmed during the optimization process.Found 2048x8-bit dual-port RAM <Mram_imem_bank_0_ram> for signal <imem_bank_0_ram>.Found 2048x8-bit dual-port RAM <Mram_imem_bank_1_ram> for signal <imem_bank_1_ram>.Found 2048x8-bit dual-port RAM <Mram_imem_bank_2_ram> for signal <imem_bank_2_ram>.Found 2048x8-bit dual-port RAM <Mram_imem_bank_3_ram> for signal <imem_bank_3_ram>.Found 2048x8-bit dual-port RAM <Mram_dmem_bank_0_ram> for signal <dmem_bank_0_ram>.Found 2048x8-bit dual-port RAM <Mram_dmem_bank_1_ram> for signal <dmem_bank_1_ram>.Found 2048x8-bit dual-port RAM <Mram_dmem_bank_2_ram> for signal <dmem_bank_2_ram>.Found 2048x8-bit dual-port RAM <Mram_dmem_bank_3_ram> for signal <dmem_bank_3_ram>.Found 32x32-bit dual-port RAM <Mram_core_deco_gprf_a_ram> for signal <core_deco_gprf_a_ram>.Found 32x32-bit dual-port RAM <Mram_core_deco_gprf_d_ram> for signal <core_deco_gprf_d_ram>.Found 32x32-bit dual-port RAM <Mram_core_deco_gprf_b_ram> for signal <core_deco_gprf_b_ram>.Register <core_ex_flush_id> equivalent to <core_ex_branch> has been removedUsing one-hot encoding for signal <core_mm_transfer_size>.Using one-hot encoding for signal <core_of_transfer_size>.Using one-hot encoding for signal <core_of_alu_src_a>.Using one-hot encoding for signal <core_of_alu_src_b>.Using one-hot encoding for signal <core_of_carry>.INFO:Xst:2117 - HDL ADVISOR - Mux Selector <core_of_alu_op> of Case statement line 1343 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:- add an 'INIT' attribute on signal <core_of_alu_op> (optimization is then done without any risk)- use the attribute 'signal_encoding user' to avoid onehot optimization- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimizationUsing one-hot encoding for signal <core_of_alu_op>.Using one-hot encoding for signal <core_of_branch_cond>.Using one-hot encoding for signal <core_ex_transfer_size>.Found 1-bit register for signal <txd_line>.Found 1-bit register for signal <txd_line2>.Found 16-bit adder for signal <$add0000> created at line 813.Found 4-bit adder for signal <$add0001> created at line 1557.Found 4-bit adder for signal <$add0002> created at line 1559.Found 4-bit adder for signal <$add0003> created at line 1599.Found 4-bit adder for signal <$add0004> created at line 1655.Found 4-bit adder for signal <$add0005> created at line 1657.Found 4-bit adder for signal <$add0006> created at line 1697.Found 20-bit adder for signal <$add0007> created at line 1757.Found 1-bit register for signal <core_deco_of_r_has_imm_high>.Found 1-bit register for signal <core_deco_of_r_hazard>.Found 16-bit register for signal <core_deco_of_r_immediate_high>.Found 32-bit register for signal <core_deco_of_r_instruction>.Found 1-bit register for signal <core_deco_of_r_mem_read>.Found 16-bit register for signal <core_deco_of_r_program_counter>.Found 5-bit register for signal <core_deco_of_r_reg_d>.Found 1-bit register for signal <core_ex_branch>.Found 32-bit register for signal <core_ex_dat_d>.Found 1-bit register for signal <core_ex_mem_read>.Found 1-bit register for signal <core_ex_mem_write>.Found 16-bit register for signal <core_ex_program_counter>.Found 3-bit register for signal <core_ex_transfer_size>.Found 32-bit register for signal <core_exeu_ex_r_alu_result>.Found 1-bit register for signal <core_exeu_ex_r_carry>.Found 1-bit register for signal <core_exeu_ex_r_flush_ex>.Found 5-bit register for signal <core_exeu_ex_r_reg_d>.Found 1-bit register for signal <core_exeu_ex_r_reg_write>.Found 16-bit register for signal <core_ftch_if_r_program_counter>.Found 32-bit register for signal <core_gprf_dat_a>.Found 32-bit register for signal <core_gprf_dat_b>.Found 32-bit register for signal <core_gprf_dat_d>.Found 32-bit register for signal <core_mm_alu_result>.Found 1-bit register for signal <core_mm_mem_read>.Found 5-bit register for signal <core_mm_reg_d>.Found 1-bit register for signal <core_mm_reg_write>.Found 3-bit register for signal <core_mm_transfer_size>.Found 7-bit register for signal <core_of_alu_op>.Found 4-bit register for signal <core_of_alu_src_a>.Found 4-bit register for signal <core_of_alu_src_b>.Found 8-bit register for signal <core_of_branch_cond>.Found 4-bit register for signal <core_of_carry>.Found 1-bit register for signal <core_of_carry_keep>.Found 1-bit register for signal <core_of_delay>.Found 32-bit register for signal <core_of_fwd_mem_result>.Found 5-bit register for signal <core_of_fwd_reg_d>.Found 1-bit register for signal <core_of_fwd_reg_write>.Found 32-bit register for signal <core_of_immediate>.Found 1-bit register for signal <core_of_mem_write>.Found 1-bit register for signal <core_of_operation>.Found 16-bit register for signal <core_of_program_counter>.Found 5-bit register for signal <core_of_reg_a>.Found 5-bit register for signal <core_of_reg_b>.Found 1-bit register for signal <core_of_reg_write>.Found 3-bit register for signal <core_of_transfer_size>.Found 20-bit register for signal <count>.Found 32-bit register for signal <dmem_bank_out>.Found 28-bit comparator greatequal for signal <dmem_ena_in$cmp_ge0000> created at line 1725.Found 32-bit comparator less for signal <dmem_ena_in$cmp_lt0000> created at line 1721.Found 32-bit register for signal <imem_bank_out>.Found 5-bit comparator equal for signal <instruction_7$cmp_eq0000> created at line 962.Found 5-bit comparator equal for signal <instruction_7$cmp_eq0001> created at line 962.Found 5-bit comparator equal for signal <instruction_7$cmp_eq0002> created at line 967.Found 32-bit register for signal <led_reg>.Found 5-bit comparator equal for signal <result_26$cmp_eq0000> created at line 274.Found 5-bit comparator equal for signal <result_28$cmp_eq0000> created at line 308.Found 5-bit comparator equal for signal <result_30$cmp_eq0000> created at line 342.Found 5-bit comparator equal for signal <result_32$cmp_eq0000> created at line 420.Found 5-bit comparator equal for signal <result_33$cmp_eq0000> created at line 432.Found 5-bit comparator equal for signal <result_35$cmp_eq0000> created at line 444.Found 5-bit comparator equal for signal <result_36$cmp_eq0000> created at line 456.Found 5-bit comparator equal for signal <result_37$cmp_eq0000> created at line 468.Found 5-bit comparator equal for signal <result_39$cmp_eq0000> created at line 503.Found 16-bit down counter for signal <uart2_enable16_counter>.Found 4-bit register for signal <uart2_rx_bitcount>.Found 4-bit register for signal <uart2_rx_count16>.Found 1-bit register for signal <uart2_rx_is_busy>.Found 8-bit register for signal <uart2_rxd_reg>.Found 4-bit register for signal <uart2_tx_bitcount>.Found 4-bit register for signal <uart2_tx_count16>.Found 9-bit register for signal <uart2_txd_reg>.Found 1-bit register for signal <uart2_uart_rxd1>.Found 1-bit register for signal <uart2_uart_rxd2>.Found 16-bit down counter for signal <uart_enable16_counter>.Found 4-bit register for signal <uart_rx_bitcount>.Found 4-bit register for signal <uart_rx_count16>.Found 1-bit register for signal <uart_rx_is_busy>.Found 1-bit register for signal <uart_rxd>.Found 1-bit register for signal <uart_rxd2>.Found 8-bit register for signal <uart_rxd_reg>.Found 4-bit register for signal <uart_tx_bitcount>.Found 4-bit subtractor for signal <uart_tx_bitcount$addsub0000> created at line 1601.Found 4-bit register for signal <uart_tx_count16>.Found 1-bit register for signal <uart_tx_is_busy>.Found 1-bit register for signal <uart_txd>.Found 9-bit register for signal <uart_txd_reg>.Found 1-bit register for signal <uart_uart_rxd1>.Found 1-bit register for signal <uart_uart_rxd2>.Summary:inferred 11 RAM(s).inferred 2 Counter(s).inferred 645 D-type flip-flop(s).inferred 10 Adder/Subtractor(s).inferred 14 Comparator(s).inferred 192 Multiplexer(s).Unit <SysTop> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# RAMs : 112048x8-bit dual-port RAM : 832x32-bit dual-port RAM : 3# Adders/Subtractors : 1016-bit adder : 120-bit adder : 134-bit adder : 14-bit adder : 64-bit subtractor : 1# Counters : 216-bit down counter : 2# Registers : 771-bit register : 2916-bit register : 520-bit register : 13-bit register : 332-bit register : 104-bit register : 105-bit register : 67-bit register : 18-bit register : 119-bit register : 1# Comparators : 1428-bit comparator greatequal : 132-bit comparator less : 15-bit comparator equal : 12# Multiplexers : 632-bit 4-to-1 multiplexer : 6# Xors : 21-bit xor2 : 132-bit xor2 : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Loading device for application Rf_Device from file '3s500e.nph' in environment /home/daniel/Applications/Xilinx/10.1/ISE.Synthesizing (advanced) Unit <SysTop>.INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_exeu_ex_r_alu_result> prevents it from being combined with the RAM <Mram_dmem_bank_1_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<1>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_dmem_bank_1_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <dmem_bank_out_1>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<1>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena> | high || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to signal <dmem_bank_out<1>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_exeu_ex_r_alu_result> prevents it from being combined with the RAM <Mram_dmem_bank_0_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<0>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_dmem_bank_0_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <dmem_bank_out_0>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<0>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena> | high || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to signal <dmem_bank_out<0>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_exeu_ex_r_alu_result> prevents it from being combined with the RAM <Mram_dmem_bank_2_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<2>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_dmem_bank_2_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <dmem_bank_out_2>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<2>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena> | high || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to signal <dmem_bank_out<2>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_mm_reg_d> prevents it from being combined with the RAM <Mram_core_deco_gprf_a_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 32-word x 32-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <core_mm_reg_write_0> | high || addrA | connected to signal <core_mm_reg_d> | || diA | connected to signal <core_deco_wb_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 32-word x 32-bit | || addrB | connected to signal <core_deco_of_comb_reg_a> | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_core_deco_gprf_a_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <core_gprf_dat_a>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 32-word x 32-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <core_mm_reg_write_0> | high || addrA | connected to signal <core_mm_reg_d> | || diA | connected to signal <core_deco_wb_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 32-word x 32-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to signal <core_deco_of_comb_reg_a> | || doB | connected to signal <core_gprf_dat_a> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_exeu_ex_r_alu_result> prevents it from being combined with the RAM <Mram_dmem_bank_3_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<3>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_dmem_bank_3_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <dmem_bank_out_3>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <dmem_sel<3>_0> | high || addrA | connected to signal <core_exeu_ex_r_alu_result> | || diA | connected to signal <core_ex_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena> | high || addrB | connected to signal <core_exeu_ex_r_alu_result> | || doB | connected to signal <dmem_bank_out<3>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_mm_reg_d> prevents it from being combined with the RAM <Mram_core_deco_gprf_d_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 32-word x 32-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <core_mm_reg_write_1> | high || addrA | connected to signal <core_mm_reg_d> | || diA | connected to signal <core_deco_wb_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 32-word x 32-bit | || addrB | connected to internal node | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_core_deco_gprf_d_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <core_gprf_dat_d>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 32-word x 32-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <core_mm_reg_write_1> | high || addrA | connected to signal <core_mm_reg_d> | || diA | connected to signal <core_deco_wb_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 32-word x 32-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to internal node | || doB | connected to signal <core_gprf_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register <core_mm_reg_d> prevents it from being combined with the RAM <Mram_core_deco_gprf_b_ram> for implementation as read-only block RAM.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 32-word x 32-bit | || clkA | connected to signal <clock> | rise || weA | connected to signal <core_mm_reg_write_2> | high || addrA | connected to signal <core_mm_reg_d> | || diA | connected to signal <core_deco_wb_dat_d> | |-----------------------------------------------------------------------| Port B || aspect ratio | 32-word x 32-bit | || addrB | connected to signal <SYSTOP_CORE_DECO_COMB_MYHDL25_sign_extend16_1_MYHDL25_sign_extend16> | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_core_deco_gprf_b_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <core_gprf_dat_b>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 32-word x 32-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <core_mm_reg_write_2> | high || addrA | connected to signal <core_mm_reg_d> | || diA | connected to signal <core_deco_wb_dat_d> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 32-word x 32-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to signal <SYSTOP_CORE_DECO_COMB_MYHDL25_sign_extend16_1_MYHDL25_sign_extend16> | || doB | connected to signal <core_gprf_dat_b> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_imem_bank_0_ram> appears to be read-only. If that was not your intent please check the write enable description.INFO:Xst - The RAM <Mram_imem_bank_0_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <imem_bank_out_0>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <GND> | high || addrA | connected to signal <core_ftch_if_comb_r_program_counter> | || diA | connected to signal <GND> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to signal <core_ftch_if_comb_r_program_counter> | || doB | connected to signal <imem_bank_out<0>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_imem_bank_1_ram> appears to be read-only. If that was not your intent please check the write enable description.INFO:Xst - The RAM <Mram_imem_bank_1_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <imem_bank_out_1>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <GND> | high || addrA | connected to signal <core_ftch_if_comb_r_program_counter> | || diA | connected to signal <GND> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to signal <core_ftch_if_comb_r_program_counter> | || doB | connected to signal <imem_bank_out<1>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_imem_bank_2_ram> appears to be read-only. If that was not your intent please check the write enable description.INFO:Xst - The RAM <Mram_imem_bank_2_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <imem_bank_out_2>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <GND> | high || addrA | connected to signal <core_ftch_if_comb_r_program_counter> | || diA | connected to signal <GND> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to signal <core_ftch_if_comb_r_program_counter> | || doB | connected to signal <imem_bank_out<2>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------INFO:Xst - The RAM <Mram_imem_bank_3_ram> appears to be read-only. If that was not your intent please check the write enable description.INFO:Xst - The RAM <Mram_imem_bank_3_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <imem_bank_out_3>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 2048-word x 8-bit | || mode | write-first | || clkA | connected to signal <clock> | rise || weA | connected to signal <GND> | high || addrA | connected to signal <core_ftch_if_comb_r_program_counter> | || diA | connected to signal <GND> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 2048-word x 8-bit | || mode | read-first | || clkB | connected to signal <clock> | rise || enB | connected to signal <dmem_ena_in> | high || addrB | connected to signal <core_ftch_if_comb_r_program_counter> | || doB | connected to signal <imem_bank_out<3>> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------Unit <SysTop> synthesized (advanced).WARNING:Xst:2677 - Node <core_of_alu_src_a_0> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <core_of_carry_0> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <core_of_alu_src_b_0> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <core_of_branch_cond_7> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <core_of_transfer_size_0> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <core_ex_transfer_size_0> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <core_mm_transfer_size_0> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_8> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_9> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_10> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_11> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_12> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_13> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_14> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_15> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_16> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_17> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_18> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_19> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_20> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_21> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_22> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_23> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_24> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_25> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_26> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_27> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_28> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_29> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_30> of sequential type is unconnected in block <SysTop>.WARNING:Xst:2677 - Node <led_reg_31> of sequential type is unconnected in block <SysTop>.=========================================================================Advanced HDL Synthesis ReportMacro Statistics# RAMs : 112048x8-bit dual-port block RAM : 832x32-bit dual-port block RAM : 3# Adders/Subtractors : 416-bit adder : 134-bit adder : 14-bit adder : 14-bit subtractor : 1# Counters : 116-bit down counter : 1# Registers : 377Flip-Flops : 377# Comparators : 1428-bit comparator greatequal : 132-bit comparator less : 15-bit comparator equal : 12# Multiplexers : 632-bit 4-to-1 multiplexer : 6# Xors : 21-bit xor2 : 132-bit xor2 : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <SysTop> ...INFO:Xst:2261 - The FF/Latch <core_of_immediate_14> in Unit <SysTop> is equivalent to the following FF/Latch, which will be removed : <core_of_reg_b_3>INFO:Xst:2261 - The FF/Latch <core_of_immediate_13> in Unit <SysTop> is equivalent to the following FF/Latch, which will be removed : <core_of_reg_b_2>INFO:Xst:2261 - The FF/Latch <core_of_immediate_12> in Unit <SysTop> is equivalent to the following FF/Latch, which will be removed : <core_of_reg_b_1>INFO:Xst:2261 - The FF/Latch <core_of_immediate_11> in Unit <SysTop> is equivalent to the following FF/Latch, which will be removed : <core_of_reg_b_0>INFO:Xst:2261 - The FF/Latch <core_of_immediate_15> in Unit <SysTop> is equivalent to the following FF/Latch, which will be removed : <core_of_reg_b_4>Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block SysTop, actual ratio is 15.FlipFlop core_mm_alu_result_1 has been replicated 1 time(s)FlipFlop core_mm_mem_read has been replicated 1 time(s)FlipFlop core_mm_transfer_size_1 has been replicated 1 time(s)FlipFlop core_mm_transfer_size_2 has been replicated 1 time(s)Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers : 392Flip-Flops : 392==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : SysTop.ngrTop Level Output File Name : SysTopOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 14Cell Usage :# BELS : 1495# GND : 1# INV : 18# LUT1 : 15# LUT2 : 114# LUT2_D : 4# LUT2_L : 1# LUT3 : 249# LUT3_D : 14# LUT3_L : 22# LUT4 : 679# LUT4_D : 56# LUT4_L : 112# MUXCY : 89# MUXF5 : 58# VCC : 1# XORCY : 62# FlipFlops/Latches : 392# FDE : 13# FDR : 15# FDRE : 358# FDS : 3# FDSE : 3# RAMS : 11# RAMB16_S36_S36 : 3# RAMB16_S9_S9 : 8# Clock Buffers : 1# BUFGP : 1# IO Buffers : 11# IBUF : 1# OBUF : 10=========================================================================Device utilization summary:---------------------------Selected Device : 3s500efg320-4Number of Slices: 678 out of 4656 14%Number of Slice Flip Flops: 391 out of 9312 4%Number of 4 input LUTs: 1284 out of 9312 13%Number of IOs: 14Number of bonded IOBs: 12 out of 232 5%IOB Flip Flops: 1Number of BRAMs: 11 out of 20 55%Number of GCLKs: 1 out of 24 4%---------------------------Partition Resource Summary:---------------------------No Partitions were found in this design.---------------------------=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clock | BUFGP | 403 |-----------------------------------+------------------------+-------+Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -4Minimum period: 13.802ns (Maximum Frequency: 72.453MHz)Minimum input arrival time before clock: 5.419nsMaximum output required time after clock: 4.283nsMaximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clock'Clock period: 13.802ns (frequency: 72.453MHz)Total number of paths / destination ports: 247273 / 1133-------------------------------------------------------------------------Delay: 13.802ns (Levels of Logic = 39)Source: core_exeu_ex_r_reg_write (FF)Destination: core_exeu_ex_r_alu_result_31 (FF)Source Clock: clock risingDestination Clock: clock risingData Path: core_exeu_ex_r_reg_write to core_exeu_ex_r_alu_result_31Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDRE:C->Q 6 0.591 0.844 core_exeu_ex_r_reg_write (core_exeu_ex_r_reg_write)LUT3:I0->O 1 0.704 0.499 _old_SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_result_3240_1 (_old_SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_result_32401)LUT3:I1->O 14 0.704 1.004 _old_SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_result_3282 (SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_MYHDL36_forward_condition)LUT4:I3->O 19 0.704 1.085 Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_a_421101_1 (Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_a_421101)MUXF5:S->O 1 0.739 0.424 Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_a_421241_SW0 (N309)LUT4:I3->O 4 0.704 0.622 _old_SYSTOP_CORE_EXEU_COMB_alu_src_a_44<0> (_old_SYSTOP_CORE_EXEU_COMB_alu_src_a_44<0>)LUT4:I2->O 1 0.704 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<1> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<1>)MUXCY:S->O 1 0.464 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<1> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<1>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<2> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<2>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30>)MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31>)XORCY:CI->O 1 0.804 0.424 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor<32> (SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<31>)LUT4:I3->O 1 0.704 0.000 _old_SYSTOP_CORE_EXEU_COMB_r_alu_result_59<31>77 (core_exeu_ex_comb_r_alu_result<31>)FDRE:D 0.308 core_exeu_ex_r_alu_result_31----------------------------------------Total 13.802ns (8.900ns logic, 4.902ns route)(64.5% logic, 35.5% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'Total number of paths / destination ports: 600 / 496-------------------------------------------------------------------------Offset: 5.419ns (Levels of Logic = 2)Source: reset (PAD)Destination: uart_enable16_counter_0 (FF)Destination Clock: clock risingData Path: reset to uart_enable16_counter_0Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 396 1.218 1.552 reset_IBUF (reset_IBUF)LUT2:I0->O 16 0.704 1.034 uart_enable16_counter_or00001 (uart_enable16_counter_or0000)FDR:R 0.911 uart_enable16_counter_0----------------------------------------Total 5.419ns (2.833ns logic, 2.586ns route)(52.3% logic, 47.7% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'Total number of paths / destination ports: 10 / 10-------------------------------------------------------------------------Offset: 4.283ns (Levels of Logic = 1)Source: txd_line2 (FF)Destination: txd_line2 (PAD)Source Clock: clock risingData Path: txd_line2 to txd_line2Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDR:C->Q 1 0.591 0.420 txd_line2 (txd_line2_OBUF)OBUF:I->O 3.272 txd_line2_OBUF (txd_line2)----------------------------------------Total 4.283ns (3.863ns logic, 0.420ns route)(90.2% logic, 9.8% route)=========================================================================Total REAL time to Xst completion: 24.00 secsTotal CPU time to Xst completion: 24.43 secs-->Total memory usage is 421724 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 102 ( 0 filtered)Number of infos : 58 ( 0 filtered)