OpenCores
URL https://opencores.org/ocsvn/myblaze/myblaze/trunk

Subversion Repositories myblaze

[/] [myblaze/] [trunk/] [system/] [uart_test_top/] [SysTop.twx] - Rev 6

Compare with Previous | Blame | View Log 

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
                                        twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
                                                           NETDELAY | 
                                                           NETSKEW | 
                                                           PATH |
                                                           DEFPERIOD |
                                                           UNCONSTPATH |
                                                           DEFPATH | 
                                                           PATH2SETUP |
                                                           UNCONSTPATH2SETUP | 
                                                           PATHCLASS | 
                                                           PATHDELAY | 
                                                           PERIOD |
                                                           FREQUENCY |
                                                           PATHBLOCK |
                                                           OFFSET |
                                                           OFFSETIN |
                                                           OFFSETINCLOCK | 
                                                           UNCONSTOFFSETINCLOCK |
                                                           OFFSETINDELAY |
                                                           OFFSETINMOD |
                                                           OFFSETOUT |
                                                           OFFSETOUTCLOCK |
                                                           UNCONSTOFFSETOUTCLOCK | 
                                                           OFFSETOUTDELAY |
                                                           OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
                                           twEndPtCnt?,
                                           twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
                                                twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
                                          fDCMJit CDATA #IMPLIED
                                          fPhaseErr CDATA #IMPLIED
                                          sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
                         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
                                          best CDATA #IMPLIED requested CDATA #IMPLIED
                                          errors CDATA #IMPLIED
                                          score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 10.1.03 Trace  (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>/home/daniel/Applications/Xilinx/10.1/ISE/bin/lin64/unwrapped/trce -ise
/home/daniel/Sources/myblaze/system/uart_test_top/uart_test_top.ise -intstyle
ise -v 3 -s 4 -xml SysTop SysTop.ncd -o SysTop.twr SysTop.pcf -ucf
/home/daniel/Sources/myblaze/rtl/uart_test_top.ucf

</twCmdLine><twDesign>SysTop.ncd</twDesign><twPCF>SysTop.pcf</twPCF><twDevInfo arch="spartan3e" pkg="fg320"><twDevName>xc3s500e</twDevName><twSpeedGrade>-4</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2008-01-09</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo>INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst twConstType="PERIOD" ><twConstHead uID="0x4232770"><twConstName UCFConstName="TIMESPEC TS_clock = PERIOD &quot;clock&quot; 20 ns HIGH 50 %;">TS_clock = PERIOD TIMEGRP &quot;clock&quot; 20 ns HIGH 50%;</twConstName><twItemCnt>247273</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>1947</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>17.967</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>2.033</twSlack><twSrc BELType="RAM">Mram_dmem_bank_3_ram.B</twSrc><twDest BELType="FF">core_exeu_ex_r_carry</twDest><twTotPathDel>17.967</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='RAM'>Mram_dmem_bank_3_ram.B</twSrc><twDest BELType='FF'>core_exeu_ex_r_carry</twDest><twLogLvls>22</twLogLvls><twSrcSite>RAMB16_X1Y6.CLKB</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clock_BUFGP</twSrcClk><twPathDel><twSite>RAMB16_X1Y6.DOB2</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">2.812</twDelInfo><twComp>Mram_dmem_bank_3_ram</twComp><twBEL>Mram_dmem_bank_3_ram.B</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y45.F1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.099</twDelInfo><twComp>dmem_bank_out&lt;3&gt;&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y45.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>N274</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;17_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.G1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.438</twDelInfo><twComp>N274</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>core_of_fwd_mem_result&lt;2&gt;</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;17</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.023</twDelInfo><twComp>core_deco_wb_dat_d&lt;2&gt;17/O</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>core_of_fwd_mem_result&lt;2&gt;</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;38</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y50.F2</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">2.532</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y50.X</twSite><twDelType>Tif5x</twDelType><twDelInfo twEdge="twRising">1.025</twDelInfo><twComp>N342</twComp><twBEL>Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G</twBEL><twBEL>Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y48.F1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.092</twDelInfo><twComp>N342</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y48.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twComp><twBEL>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y45.G2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.944</twDelInfo><twComp>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y45.COUT</twSite><twDelType>Topcyg</twDelType><twDelInfo twEdge="twRising">1.001</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;1&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut&lt;3&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y46.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y46.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;3&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;4&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;5&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y47.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y47.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;5&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;6&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y48.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y48.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;7&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;8&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;9&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y49.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y49.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;9&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;10&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y50.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y50.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;11&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;12&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;13&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y51.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;13&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y51.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;13&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;14&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y52.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y52.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;15&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;16&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;17&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y53.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;17&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y53.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;17&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;18&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y54.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y54.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;19&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;20&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;21&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y55.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;21&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y55.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;21&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;22&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;23&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y56.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;23&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y56.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;23&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;24&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;25&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y57.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;25&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y57.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;25&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;26&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;27&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y58.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;27&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y58.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;27&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;28&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;29&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y59.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;29&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y59.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;29&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;30&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;31&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y60.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;31&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y60.XB</twSite><twDelType>Tcinxb</twDelType><twDelInfo twEdge="twRising">0.404</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;31&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;32&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y53.F1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.072</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;32&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y53.CLK</twSite><twDelType>Tfck</twDelType><twDelInfo twEdge="twRising">0.892</twDelInfo><twComp>core_exeu_ex_r_carry</twComp><twBEL>_old_SYSTOP_CORE_EXEU_COMB_r_carry_57</twBEL><twBEL>core_exeu_ex_r_carry</twBEL></twPathDel><twLogDel>10.767</twLogDel><twRouteDel>7.200</twRouteDel><twTotDel>17.967</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">clock_BUFGP</twDestClk><twPctLog>59.9</twPctLog><twPctRoute>40.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>2.160</twSlack><twSrc BELType="RAM">Mram_dmem_bank_3_ram.B</twSrc><twDest BELType="FF">core_exeu_ex_r_alu_result_30</twDest><twTotPathDel>17.828</twTotPathDel><twClkSkew dest = "0.075" src = "0.087">0.012</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='RAM'>Mram_dmem_bank_3_ram.B</twSrc><twDest BELType='FF'>core_exeu_ex_r_alu_result_30</twDest><twLogLvls>21</twLogLvls><twSrcSite>RAMB16_X1Y6.CLKB</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clock_BUFGP</twSrcClk><twPathDel><twSite>RAMB16_X1Y6.DOB2</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">2.812</twDelInfo><twComp>Mram_dmem_bank_3_ram</twComp><twBEL>Mram_dmem_bank_3_ram.B</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y45.F1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.099</twDelInfo><twComp>dmem_bank_out&lt;3&gt;&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y45.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>N274</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;17_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.G1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.438</twDelInfo><twComp>N274</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>core_of_fwd_mem_result&lt;2&gt;</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;17</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.023</twDelInfo><twComp>core_deco_wb_dat_d&lt;2&gt;17/O</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>core_of_fwd_mem_result&lt;2&gt;</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;38</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y50.F2</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">2.532</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y50.X</twSite><twDelType>Tif5x</twDelType><twDelInfo twEdge="twRising">1.025</twDelInfo><twComp>N342</twComp><twBEL>Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G</twBEL><twBEL>Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y48.F1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.092</twDelInfo><twComp>N342</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y48.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twComp><twBEL>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y45.G2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.944</twDelInfo><twComp>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y45.COUT</twSite><twDelType>Topcyg</twDelType><twDelInfo twEdge="twRising">1.001</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;1&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut&lt;3&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y46.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y46.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;3&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;4&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;5&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y47.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y47.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;5&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;6&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y48.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y48.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;7&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;8&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;9&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y49.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y49.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;9&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;10&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y50.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y50.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;11&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;12&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;13&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y51.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;13&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y51.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;13&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;14&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y52.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y52.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;15&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;16&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;17&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y53.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;17&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y53.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;17&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;18&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y54.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y54.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;19&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;20&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;21&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y55.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;21&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y55.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;21&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;22&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;23&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y56.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;23&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y56.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;23&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;24&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;25&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y57.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;25&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y57.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;25&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;26&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;27&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y58.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;27&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y58.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;27&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;28&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;29&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y59.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;29&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y59.Y</twSite><twDelType>Tciny</twDelType><twDelInfo twEdge="twRising">0.869</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;29&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;30&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor&lt;31&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y62.F3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.586</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;30&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y62.CLK</twSite><twDelType>Tfck</twDelType><twDelInfo twEdge="twRising">0.892</twDelInfo><twComp>core_exeu_ex_r_alu_result&lt;30&gt;</twComp><twBEL>_old_SYSTOP_CORE_EXEU_COMB_result_53&lt;30&gt;63</twBEL><twBEL>core_exeu_ex_r_alu_result_30</twBEL></twPathDel><twLogDel>11.114</twLogDel><twRouteDel>6.714</twRouteDel><twTotDel>17.828</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">clock_BUFGP</twDestClk><twPctLog>62.3</twPctLog><twPctRoute>37.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>2.225</twSlack><twSrc BELType="RAM">Mram_dmem_bank_3_ram.B</twSrc><twDest BELType="FF">core_exeu_ex_r_alu_result_22</twDest><twTotPathDel>17.753</twTotPathDel><twClkSkew dest = "0.065" src = "0.087">0.022</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='RAM'>Mram_dmem_bank_3_ram.B</twSrc><twDest BELType='FF'>core_exeu_ex_r_alu_result_22</twDest><twLogLvls>17</twLogLvls><twSrcSite>RAMB16_X1Y6.CLKB</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clock_BUFGP</twSrcClk><twPathDel><twSite>RAMB16_X1Y6.DOB2</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">2.812</twDelInfo><twComp>Mram_dmem_bank_3_ram</twComp><twBEL>Mram_dmem_bank_3_ram.B</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y45.F1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.099</twDelInfo><twComp>dmem_bank_out&lt;3&gt;&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y45.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>N274</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;17_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.G1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.438</twDelInfo><twComp>N274</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>core_of_fwd_mem_result&lt;2&gt;</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;17</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.023</twDelInfo><twComp>core_deco_wb_dat_d&lt;2&gt;17/O</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>core_of_fwd_mem_result&lt;2&gt;</twComp><twBEL>core_deco_wb_dat_d&lt;2&gt;38</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y50.F2</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">2.532</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y50.X</twSite><twDelType>Tif5x</twDelType><twDelInfo twEdge="twRising">1.025</twDelInfo><twComp>N342</twComp><twBEL>Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G</twBEL><twBEL>Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y48.F1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.092</twDelInfo><twComp>N342</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y48.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twComp><twBEL>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y45.G2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.944</twDelInfo><twComp>_old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y45.COUT</twSite><twDelType>Topcyg</twDelType><twDelInfo twEdge="twRising">1.001</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;1&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut&lt;3&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y46.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y46.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;3&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;4&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;5&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y47.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y47.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;5&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;6&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y48.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y48.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;7&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;8&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;9&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y49.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y49.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;9&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;10&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y50.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y50.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;11&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;12&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;13&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y51.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;13&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y51.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;13&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;14&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y52.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y52.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;15&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;16&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;17&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y53.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;17&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y53.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;17&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;18&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y54.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y54.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;19&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;20&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;21&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y55.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;21&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y55.Y</twSite><twDelType>Tciny</twDelType><twDelInfo twEdge="twRising">0.869</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;21&gt;</twComp><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy&lt;22&gt;</twBEL><twBEL>Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor&lt;23&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X44Y60.F2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.983</twDelInfo><twComp>SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add&lt;22&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X44Y60.CLK</twSite><twDelType>Tfck</twDelType><twDelInfo twEdge="twRising">0.892</twDelInfo><twComp>core_exeu_ex_r_alu_result&lt;22&gt;</twComp><twBEL>_old_SYSTOP_CORE_EXEU_COMB_result_53&lt;22&gt;63</twBEL><twBEL>core_exeu_ex_r_alu_result_22</twBEL></twPathDel><twLogDel>10.642</twLogDel><twRouteDel>7.111</twRouteDel><twTotDel>17.753</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">clock_BUFGP</twDestClk><twPctLog>59.9</twPctLog><twPctRoute>40.1</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twUnmetConstCnt>0</twUnmetConstCnt><twDataSheet twNameLen="15"><twClk2SUList twDestWidth = "5"><twDest>clock</twDest><twClk2SU><twSrc>clock</twSrc><twRiseRise>17.967</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum><twErrCnt>0</twErrCnt><twScore>0</twScore><twConstCov><twPathCnt>247273</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>5595</twConnCnt></twConstCov><twStats><twMinPer>17.967</twMinPer><twFootnote number="1" /><twMaxFreq>55.658</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Sun Nov 21 23:39:25 2010 </twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 248 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.