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Release 10.1.03 Map K.39 (lin64)
Xilinx Mapping Report File for Design 'SysTop'

Design Information
------------------
Command Line   : map -ise
/home/daniel/Sources/myblaze/system/uart_test_top/uart_test_top.ise -intstyle
ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o SysTop_map.ncd
SysTop.ngd SysTop.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
Mapped Date    : Sun Nov 21 23:39:00 2010

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:           391 out of   9,312    4%
  Number of 4 input LUTs:             1,262 out of   9,312   13%
Logic Distribution:
  Number of occupied Slices:            702 out of   4,656   15%
    Number of Slices containing only related logic:     702 out of     702 100%
    Number of Slices containing unrelated logic:          0 out of     702   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       1,277 out of   9,312   13%
    Number used as logic:             1,262
    Number used as a route-thru:         15
  Number of bonded IOBs:                 13 out of     232    5%
    IOB Flip Flops:                       1
  Number of RAMB16s:                     11 out of      20   55%
  Number of BUFGMUXs:                     1 out of      24    4%

Peak Memory Usage:  426 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   3 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network rxd_line2 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
   more times for the following (max. 5 shown):
   rxd_line_IBUF
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:367 - The signal <rxd_line_IBUF> is incomplete. The
   signal does not drive any load pins in the design.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE            BLOCK
GND             XST_GND
VCC             XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+-------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Strength | Rate |              |          | Delay    |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| clock                              | IBUF             | INPUT     | LVCMOS33             |          |      |              |          | 0 / 0    |
| leds<0>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<1>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<2>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<3>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<4>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<5>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<6>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| leds<7>                            | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| reset                              | IBUF             | INPUT     | LVTTL                |          |      |              | PULLDOWN | 0 / 0    |
| rxd_line                           | IBUF             | INPUT     | LVTTL                |          |      |              |          | 0 / 0    |
| txd_line                           | IOB              | OUTPUT    | LVTTL                | 8        | SLOW |              |          | 0 / 0    |
| txd_line2                          | IOB              | OUTPUT    | LVCMOS25             | 12       | SLOW | OFF1         |          | 0 / 0    |
+-------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.

Section 14 - Utilization by Hierarchy
-------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module             | Partition | Slices        | Slice Reg     | LUTs          | LUTRAM        | BRAM      | MULT18X18 | BUFG  | DCM   | Full Hierarchical  |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
| SysTop/            |           | 702/702       | 391/391       | 1277/1277     | 0/0           | 11/11     | 0/0       | 1/1   | 0/0   | SysTop             |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+

* Slices can be packed with basic elements from multiple hierarchies.
  Therefore, a slice will be counted in every hierarchical module
  that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/<B>.
   <A> is the number of elements that belong to that specific hierarchical module.
   <B> is the total number of elements from that hierarchical module and any lower level
   hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.