Subversion Repositories myhdl_lfsr

-- File: generated/lfsr_1024.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_1024 is
    port (
        reset: in std_logic;
        clock: in std_logic;
        lfsr_out: out unsigned(1023 downto 0)
    );
end entity lfsr_1024;
 
 
architecture MyHDL of lfsr_1024 is
 
 
 
 
 
signal reg_internal: unsigned(1023 downto 0);
 
begin
 
 
 
 
 
LFSR_1024_LFSR_LOGIC: process (clock, reset) is
begin
    if (reset = '1') then
        reg_internal <= unsigned'"0010101001100110010111000110010110001000111011111000011010001110000111011011010010100011100001110100000111101001110110010000010111110110001010011001111001111111011101010110011001011101100111110011000000100011100111111010010010011110110011000001101100110100110000010101111001110010100110111001001011101101110111010100111010001110110101101010010011011111010011010001101001011110110010100100010001011010001001110110011001011001011111101011100001000000111011110001110111111110111111111000100011110110100011000000101110110001100000101111000101111010010100000001011100001100110010101000100001100110011001011101010011110100011001101110101100111101100110101010011110100111100001110001100001100110010000000111001100001011101101011000100111010000001010110000000011001000111010000001110001000100010110111000100011001101011100111000000101000010010010100011110001001001010011010110000001111000001100101010111101010111010101000100101001001111100000101110111111011000000011010010001010011011001001011101110010011010001001111001111000111110";
    elsif rising_edge(clock) then
        if (reg_internal(0) = '1') then
            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1000000001000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
        else
            reg_internal <= shift_right(reg_internal, 1);
        end if;
    end if;
end process LFSR_1024_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;