URL
https://opencores.org/ocsvn/myhdl_lfsr/myhdl_lfsr/trunk
Subversion Repositories myhdl_lfsr
[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [VHDL/] [lfsr_4.vhd] - Rev 2
Compare with Previous | Blame | View Log
-- File: generated/lfsr_4.vhd -- Generated by MyHDL 0.9.0 -- Date: Thu Jan 11 17:29:05 2018 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_090.all; entity lfsr_4 is port ( reset: in std_logic; clock: in std_logic; lfsr_out: out unsigned(3 downto 0) ); end entity lfsr_4; architecture MyHDL of lfsr_4 is constant tap_const__val: integer := 12; signal reg_internal: unsigned(3 downto 0); begin LFSR_4_LFSR_LOGIC: process (clock, reset) is begin if (reset = '1') then reg_internal <= to_unsigned(3, 4); elsif rising_edge(clock) then if (reg_internal(0) = '1') then reg_internal <= (shift_right(reg_internal, 1) xor to_unsigned(tap_const__val, 4)); else reg_internal <= shift_right(reg_internal, 1); end if; end if; end process LFSR_4_LFSR_LOGIC; lfsr_out <= reg_internal; end architecture MyHDL;