Subversion Repositories myhdl_lfsr

-- File: generated/lfsr_513.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_513 is
    port (
        reset: in std_logic;
        clock: in std_logic;
        lfsr_out: out unsigned(512 downto 0)
    );
end entity lfsr_513;
 
 
architecture MyHDL of lfsr_513 is
 
 
 
 
 
signal reg_internal: unsigned(512 downto 0);
 
begin
 
 
 
 
 
LFSR_513_LFSR_LOGIC: process (clock, reset) is
begin
    if (reset = '1') then
        reg_internal <= unsigned'"000111001001101111000110110000101111001101110001101011000000100111000100000110000000101001011000100100100111111101100000010010110101001010111000111010110110010110011011010111111010010001001011100100010110011101101111010000100001010101100010101100011111101100011010100011101001101001100010010100100011000000000000110111000111110100000111000010001101110100011100010011001111101000101101100111000000010010110000000010010001101000100000100010010100000110001111110111101011111001111100101010100110110001001111101001011";
    elsif rising_edge(clock) then
        if (reg_internal(0) = '1') then
            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
        else
            reg_internal <= shift_right(reg_internal, 1);
        end if;
    end if;
end process LFSR_513_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;