URL
https://opencores.org/ocsvn/myhdl_lfsr/myhdl_lfsr/trunk
Subversion Repositories myhdl_lfsr
[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [lfsr_1024.v] - Rev 2
Compare with Previous | Blame | View Log
// File: generated/lfsr_1024.v // Generated by MyHDL 0.9.0 // Date: Thu Jan 11 17:13:37 2018 `timescale 1ns/10ps module lfsr_1024 ( reset, clock, out ); input reset; input clock; output [1023:0] out; wire [1023:0] out; reg [1023:0] reg_internal; always @(posedge clock, posedge reset) begin: LFSR_1024_LFSR_LOGIC if (reset == 1) begin reg_internal <= 42082963438100842300011049632051513817286471381842424552588007902956694699216501563006494012496102355182406742128207496350734846251097969585360161454465559354154952828254567238737101599975418053047520322724235803065707102362869726195382228521523577556400186749615420832071378999503677442075829106239445563864; end else begin if ((reg_internal[0] == 1)) begin reg_internal <= ((reg_internal >>> 1) ^ 1025'h8040030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000); end else begin reg_internal <= (reg_internal >>> 1); end end end assign out = reg_internal; endmodule