URL
https://opencores.org/ocsvn/myhdl_lfsr/myhdl_lfsr/trunk
Subversion Repositories myhdl_lfsr
[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [lfsr_768.v] - Rev 2
Compare with Previous | Blame | View Log
// File: generated/lfsr_768.v // Generated by MyHDL 0.9.0 // Date: Thu Jan 11 17:13:37 2018 `timescale 1ns/10ps module lfsr_768 ( reset, clock, out ); input reset; input clock; output [767:0] out; wire [767:0] out; reg [767:0] reg_internal; always @(posedge clock, posedge reset) begin: LFSR_768_LFSR_LOGIC if (reset == 1) begin reg_internal <= 291143584868681772471303593185392365086698651189288315740359449674211451644149266507835960236242873226233363457348348077181486946179549007244965206177640157865466997687371991268069128700722368070295529878987798774955141357885005915; end else begin if ((reg_internal[0] == 1)) begin reg_internal <= ((reg_internal >>> 1) ^ 769'h880050000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000); end else begin reg_internal <= (reg_internal >>> 1); end end end assign out = reg_internal; endmodule