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==== System Configuration Information Memory (SYSINFO)

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|=======================
| Hardware source file(s): | neorv32_sysinfo.vhd | 
| Software driver file(s): | neorv32.h |
| Top entity port:         | none | 
| Configuration generics:  | * | most of the top's configuration generics
| CPU interrupts:          | none | 
|=======================

**Theory of Operation**

The SYSINFO allows the application software to determine the setting of most of the processor's top entity
generics that are related to processor/SoC configuration. All registers of this unit are read-only.

This device is always implemented - regardless of the actual hardware configuration. The bootloader as well
as the NEORV32 software runtime environment require information from this device (like memory layout
and default clock speed) for correct operation.

[NOTE]
Any write access to the SYSINFO module will raise a store bus error exception. The <<_internal_bus_monitor_buskeeper>>
will signal a "DEVICE ERROR" in this case.


.SYSINFO register map (`struct NEORV32_SYSINFO`)
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|=======================
| Address | Name [C] | Function
| `0xffffffe0` | `NEORV32_SYSINFO.CLK`         | clock speed in Hz (via top's <<_clock_frequency>> generic)
| `0xffffffe4` | `NEORV32_SYSINFO.CPU`         | specific CPU configuration (see <<_sysinfo_cpu_configuration>>)
| `0xffffffe8` | `NEORV32_SYSINFO.SOC`         | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
| `0xffffffec` | `NEORV32_SYSINFO.CACHE`       | cache configuration information (see <<_sysinfo_cache_configuration>>)
| `0xfffffff0` | `NEORV32_SYSINFO.ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
| `0xfffffff4` | `NEORV32_SYSINFO.IMEM_SIZE`   | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic)
| `0xfffffff8` | `NEORV32_SYSINFO.DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant)
| `0xfffffffc` | `NEORV32_SYSINFO.DMEM_SIZE`   | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic)
|=======================


===== SYSINFO - CPU Configuration

._SYSINFO_CPU_ bits
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|=======================
| Bit | Name [C] | Function
| `0`  | _SYSINFO_CPU_ZICSR_     | `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
| `1`  | _SYSINFO_CPU_ZIFENCEI_  | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
| `2`  | _SYSINFO_CPU_ZMMUL_     | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
| `5`  | _SYSINFO_CPU_ZFINX_     | `Zfinx` extension (`F` sub-/alternative-extension) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
| `6`  | _SYSINFO_CPU_ZXSCNT_    | Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
| `7`  | _SYSINFO_CPU_ZXNOCNT_   | Custom extension - _NO_ CPU counters: `[m]cycle` & `[m]instret` CSRs are NOT available at all when set (via top's <<_cpu_cnt_width>> generic)
| `8`  | _SYSINFO_CPU_PMP_       | `PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
| `9`  | _SYSINFO_CPU_HPM_       | `HPM` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
| `10` | _SYSINFO_CPU_DEBUGMODE_ | RISC-V CPU `debug_mode` available when set (via top's <<_on_chip_debugger_en>> generic)
| `30  | _SYSINFO_CPU_FASTMUL_   | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
| `31` | _SYSINFO_CPU_FASTSHIFT_ | fast shifts available when set (via top's <<_fast_shift_en>> generic)
|=======================


===== SYSINFO - SoC Configuration

._SYSINFO_SOC_ bits
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|=======================
| Bit | Name [C] | Function
| `0`  | _SYSINFO_SOC_BOOTLOADER_       | set if the processor-internal bootloader is implemented (via top's <<_int_bootloader_en>> generic)
| `1`  | _SYSINFO_SOC_MEM_EXT_          | set if the external Wishbone bus interface is implemented (via top's <<_mem_ext_en>> generic)
| `2`  | _SYSINFO_SOC_MEM_INT_IMEM_     | set if the processor-internal DMEM implemented (via top's <<_mem_int_dmem_en>> generic)
| `3`  | _SYSINFO_SOC_MEM_INT_DMEM_     | set if the processor-internal IMEM is implemented (via top's <<_mem_int_imem_en>> generic)
| `4`  | _SYSINFO_SOC_MEM_EXT_ENDIAN_   | set if external bus interface uses BIG-endian byte-order (via top's <<_mem_ext_big_endian>> generic)
| `5`  | _SYSINFO_SOC_ICACHE_           | set if processor-internal instruction cache is implemented (via top's <<_icache_en>> generic)
| `13` | _SYSINFO_SOC_IS_SIM_           | set if processor is being **simulated** (⚠️ not guaranteed)
| `14` | _SYSINFO_SOC_OCD_              | set if on-chip debugger implemented (via top's <<_on_chip_debugger_en>> generic)
| `15` | _SYSINFO_SOC_HW_RESET_         | set if a dedicated hardware reset of all core registers is implemented (via package's `dedicated_reset_c` constant)
| `16` | _SYSINFO_SOC_IO_GPIO_          | set if the GPIO is implemented (via top's <<_io_gpio_en>> generic)
| `17` | _SYSINFO_SOC_IO_MTIME_         | set if the MTIME is implemented (via top's <<_io_mtime_en>> generic)
| `18` | _SYSINFO_SOC_IO_UART0_         | set if the primary UART0 is implemented (via top's <<_io_uart0_en>> generic)
| `19` | _SYSINFO_SOC_IO_SPI_           | set if the SPI is implemented (via top's <<_io_spi_en>> generic)
| `20` | _SYSINFO_SOC_IO_TWI_           | set if the TWI is implemented (via top's <<_io_twi_en>> generic)
| `21` | _SYSINFO_SOC_IO_PWM_           | set if the PWM is implemented (via top's <<_io_pwm_num_ch>> generic)
| `22` | _SYSINFO_SOC_IO_WDT_           | set if the WDT is implemented (via top's <<_io_wdt_en>> generic)
| `23` | _SYSINFO_SOC_IO_CFS_           | set if the custom functions subsystem is implemented (via top's <<_io_cfs_en>> generic)
| `24` | _SYSINFO_SOC_IO_TRNG_          | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic)
| `25` | _SYSINFO_SOC_IO_SLINK_         | set if the SLINK is implemented (via top's <<_slink_num_tx>> and/or <<_slink_num_rx>> generics)
| `26` | _SYSINFO_SOC_IO_UART1_         | set if the secondary UART1 is implemented (via top's <<_io_uart1_en>> generic)
| `27` | _SYSINFO_SOC_IO_NEOLED_        | set if the NEOLED is implemented (via top's <<_io_neoled_en>> generic)
| `28` | _SYSINFO_SOC_IO_XIRQ_          | set if the XIRQ is implemented (via top's <<_xirq_num_ch>> generic)
| `29` | _SYSINFO_SOC_IO_GPTMR_         | set if the GPTMR is implemented (via top's <<_io_gptmr_en>> generic)
| `30` | _SYSINFO_SOC_IO_XIP_           | set if the XIP module is implemented (via top's <<_io_xip_en>> generic)
|=======================


===== SYSINFO - Cache Configuration

[NOTE]
Bit fields in this register are set to all-zero if the according cache is not implemented.

._SYSINFO_CACHE_ bits
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|=======================
| Bit      | Name [C] | Function
| `3:0`    | _SYSINFO_CACHE_IC_BLOCK_SIZE_3_ : _SYSINFO_CACHE_IC_BLOCK_SIZE_0_       | _log2_(i-cache block size in bytes), via top's <<_icache_block_size>> generic
| `7:4`    | _SYSINFO_CACHE_IC_NUM_BLOCKS_3_ : _SYSINFO_CACHE_IC_NUM_BLOCKS_0_       | _log2_(i-cache number of cache blocks), via top's <<_icache_num_blocks>> generic
| `11:9`   | _SYSINFO_CACHE_IC_ASSOCIATIVITY_3_ : _SYSINFO_CACHE_IC_ASSOCIATIVITY_0_ | _log2_(i-cache associativity), via top's <<_icache_associativity>> generic
| `15:12`  | _SYSINFO_CACHE_IC_REPLACEMENT_3_ : _SYSINFO_CACHE_IC_REPLACEMENT_0_     | i-cache replacement policy (`0001` = LRU if associativity > 0)
| `32:16`  | -                                                                       | zero, reserved for d-cache
|=======================