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==== External Interrupt Controller (XIRQ)

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|=======================
| Hardware source file(s): | neorv32_xirq.vhd |
| Software driver file(s): | neorv32_xirq.c |
|                          | neorv32_xirq.h |
| Top entity port:         | `xirq_i` | IRQ input (up to 32-bit)
| Configuration generics:  | _XIRQ_NUM_CH_           | Number of IRQs to implement (0..32)
|                          | _XIRQ_TRIGGER_TYPE_     | IRQ trigger type configuration
|                          | _XIRQ_TRIGGER_POLARITY_ | IRQ trigger polarity configuration
| CPU interrupts:          | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
|=======================

The eXternal interrupt controller provides a simple mechanism to implement up to 32 processor-external interrupt
request signals. The external IRQ requests are prioritized, queued and signaled to the CPU via a
single _CPU fast interrupt request_.

**Theory of Operation**

The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in `xirq_i`
represents one interrupt channel. An interrupt channel is enabled by setting the according bit in the
interrupt enable register _XIRQ_IER_.

If the configured trigger (see below) of an enabled channel fires, the request is stored into an internal buffer.
This buffer is available via the interrupt pending register _XIRQ_IPR_. A `1` in this register indicates that the
corresponding interrupt channel has fired but has not yet been serviced (so it is pending). Pending IRQs can be
cleared by writing `1` to the according pending bit. As soon as there is a least one pending interrupt in the
buffer, an interrupt request is send to the CPU.

The CPU can determine firing interrupt request either by checking the bits in the _XIRQ_IPR_ register, which show all
pending interrupt and does not prioritize, or by reading the interrupt source _XIRQ_SCR_ register.
This register provides a 5-bit wide ID (0..31) that shows the interrupt request with _highest priority_.
Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
This priority assignment is fixed and cannot be altered by software.
The CPU can use the ID from _XIRQ_SCR_ to service IRQ according to their priority. To acknowledge the according
interrupt the CPU can write `1 << XIRQ_SCR` to _XIRQ_IPR_.

**IRQ Trigger Configuration**

The controller does not provide a configuration option to define the IRQ triggers _during runtime_. Instead, two
generics are provided to configure the trigger of each interrupt channel before synthesis: the _XIRQ_TRIGGER_TYPE_
and _XIRQ_TRIGGER_POLARITY_ generic. Both generics are 32 bit wide representing one bit per interrupt channel. If
less than 32 interrupt channels are implemented the remaining configuration bits are ignored.

_XIRQ_TRIGGER_TYPE_ is used to define the general trigger type. This can either be _level-triggered_ (`0`) or
_edge-triggered_ (`1`). _XIRQ_TRIGGER_POLARITY_ is used to configure the polarity of the trigger: a `0` defines
low-level or falling-edge and a `1` defines high-level or a rising-edge.

.Example trigger configuration: channel 0 for rising-edge, IRQ channels 1 to 31 for high-level
[source, vhdl]
----
XIRQ_TRIGGER_TYPE     => x"00000001";  
XIRQ_TRIGGER_POLARITY => x"ffffffff";  
----

.XIRQ register map
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|=======================
| Address | Name [C] | Bit(s) | R/W | Function
| `0xffffff80` | _XIRQ_IER_ | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned)
| `0xffffff84` | _XIRQ_IPR_ | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 1 to a bit clears according interrupt; writing _any_ value acknowledges the _current_ CPU interrupt
| `0xffffff88` | _XIRQ_SCR_ |  `4:0` | r/- | Channel id (0..31) of firing IRQ (prioritized!)
| `0xffffff8c` | -          | `31:0` | r/- | _reserved_, read as zero
|=======================