Subversion Repositories neorv32

// #################################################################################################
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >>                                   #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_cpu.c
 * @author Stephan Nolting
 * @brief CPU Core Functions HW driver source file.
 **************************************************************************/
 
#include "neorv32.h"
#include "neorv32_cpu.h"
 
 
/**********************************************************************//**
 * Enable/disable CPU extension during runtime via the 'misa' CSR.
 *
 * @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions.
 *
 * @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum.
 * @param[in] state Set 1 to enable the selected extension, set 0 to disable it;
 * return 0 if success, 1 if error (invalid sel or extension cannot be enabled).
 **************************************************************************/
int neorv32_cpu_switch_extension(int sel, int state) {
 
  // get current misa setting
  uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA);
  uint32_t misa_prev = misa_curr;
 
  // abort if misa.z is cleared
  if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) {
    return 1;
  }
 
  // out of range?
  if (sel > 25) {
    return 1;
  }
 
  // enable/disable selected extension
  if (state & 1) {
    misa_curr |= (1 << sel);
  }
  else {
    misa_curr &= ~(1 << sel);
  }
 
  // try updating misa
  neorv32_cpu_csr_write(CSR_MISA, misa_curr);
  asm volatile("fence.i"); // required to flush prefetch buffers
  asm volatile("nop");
 
  // dit it work?
  if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) {
    return 1; // nope
  }
  else {
    return 0; // fine
  }
}
 
 
/**********************************************************************//**
 * Enable specific CPU interrupt.
 *
 * @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
 * return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
 
  if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
    return 1;
  }
 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
  asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
  return 0;
}
 
 
/**********************************************************************//**
 * Disable specific CPU interrupt.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
 * return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
 
  if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
    return 1;
  }
 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
  asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
  return 0;
}
 
 
/**********************************************************************//**
 * Simple delay function (not very precise) using busy wait.
 *
 * @param[in] time_ms Time in ms to wait.
 **************************************************************************/
void neorv32_cpu_delay_ms(uint32_t time_ms) {
 
  uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
  clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
  uint32_t cnt = clock_speed * time_ms;
 
  // one iteration = ~30 cycles
  while (cnt) {
    asm volatile("nop");
    asm volatile("nop");
    asm volatile("nop");
    asm volatile("nop");
    cnt--;
  }
}