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<?xml version="1.0" encoding="utf-8"?><device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" ><vendor>stnolting</vendor><name>neorv32</name><series>RISC-V</series><version>1.6.4</version><description>The NEORV32 RISC-V Processor</description><!-- CPU core --><cpu><name>NEORV32</name><revision>r2p0</revision><endian>little</endian><mpuPresent>true</mpuPresent><fpuPresent>true</fpuPresent><fpuDP>false</fpuDP><dspPresent>false</dspPresent><icachePresent>true</icachePresent><dcachePresent>true</dcachePresent><nvicPrioBits>0</nvicPrioBits><vendorSystickConfig>false</vendorSystickConfig></cpu><!-- defaults for all peripherals --><addressUnitBits>8</addressUnitBits><width>32</width><size>32</size><access>read-write</access><resetValue>0x00000000</resetValue><resetMask>0x00000000</resetMask> <!-- default IO devices do not have a dedicated reset --><!-- Peripherals --><peripherals><!-- CFS --><peripheral><name>CFS</name><description>Custom functions subsystem</description><groupName>CFS</groupName><baseAddress>0xFFFFFE00</baseAddress><interrupt><name>CFS_FIRQ</name><value>1</value></interrupt><addressBlock><offset>0</offset><size>0x80</size><usage>registers</usage></addressBlock><registers><register><name>REG0</name><description>Application-defined</description><addressOffset>0x00</addressOffset></register><register><name>REG1</name><description>Application-defined</description><addressOffset>0x04</addressOffset></register><register><name>REG2</name><description>Application-defined</description><addressOffset>0x08</addressOffset></register><register><name>REG3</name><description>Application-defined</description><addressOffset>0x0C</addressOffset></register><register><name>REG4</name><description>Application-defined</description><addressOffset>0x10</addressOffset></register><register><name>REG5</name><description>Application-defined</description><addressOffset>0x14</addressOffset></register><register><name>REG6</name><description>Application-defined</description><addressOffset>0x18</addressOffset></register><register><name>REG7</name><description>Application-defined</description><addressOffset>0x1C</addressOffset></register><register><name>REG8</name><description>Application-defined</description><addressOffset>0x20</addressOffset></register><register><name>REG9</name><description>Application-defined</description><addressOffset>0x24</addressOffset></register><register><name>REG10</name><description>Application-defined</description><addressOffset>0x28</addressOffset></register><register><name>REG11</name><description>Application-defined</description><addressOffset>0x2C</addressOffset></register><register><name>REG12</name><description>Application-defined</description><addressOffset>0x30</addressOffset></register><register><name>REG13</name><description>Application-defined</description><addressOffset>0x34</addressOffset></register><register><name>REG14</name><description>Application-defined</description><addressOffset>0x38</addressOffset></register><register><name>REG15</name><description>Application-defined</description><addressOffset>0x3C</addressOffset></register><register><name>REG16</name><description>Application-defined</description><addressOffset>0x40</addressOffset></register><register><name>REG17</name><description>Application-defined</description><addressOffset>0x44</addressOffset></register><register><name>REG18</name><description>Application-defined</description><addressOffset>0x48</addressOffset></register><register><name>REG19</name><description>Application-defined</description><addressOffset>0x4C</addressOffset></register><register><name>REG20</name><description>Application-defined</description><addressOffset>0x50</addressOffset></register><register><name>REG21</name><description>Application-defined</description><addressOffset>0x54</addressOffset></register><register><name>REG22</name><description>Application-defined</description><addressOffset>0x58</addressOffset></register><register><name>REG23</name><description>Application-defined</description><addressOffset>0x5C</addressOffset></register><register><name>REG24</name><description>Application-defined</description><addressOffset>0x60</addressOffset></register><register><name>REG25</name><description>Application-defined</description><addressOffset>0x64</addressOffset></register><register><name>REG26</name><description>Application-defined</description><addressOffset>0x68</addressOffset></register><register><name>REG27</name><description>Application-defined</description><addressOffset>0x6C</addressOffset></register><register><name>REG28</name><description>Application-defined</description><addressOffset>0x70</addressOffset></register><register><name>REG29</name><description>Application-defined</description><addressOffset>0x74</addressOffset></register><register><name>REG30</name><description>Application-defined</description><addressOffset>0x78</addressOffset></register><register><name>REG31</name><description>Application-defined</description><addressOffset>0x7C</addressOffset></register></registers></peripheral><!-- PWM --><peripheral><name>PWM</name><description>Pulse-width modulation controller</description><groupName>PWM</groupName><baseAddress>0xFFFFFE80</baseAddress><addressBlock><offset>0</offset><size>0x40</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>PWM_CTRL_EN</name><bitRange>[0:0]</bitRange><description>PWM controller enable flag</description></field><field><name>PWM_CTRL_PRSCx</name><bitRange>[3:1]</bitRange><description>Clock prescaler select</description></field></fields></register><register><name>DUTY0</name><description>Duty cycle register 0</description><addressOffset>0x04</addressOffset></register><register><name>DUTY1</name><description>Duty cycle register 1</description><addressOffset>0x08</addressOffset></register><register><name>DUTY2</name><description>Duty cycle register 2</description><addressOffset>0x0C</addressOffset></register><register><name>DUTY3</name><description>Duty cycle register 3</description><addressOffset>0x10</addressOffset></register><register><name>DUTY4</name><description>Duty cycle register 4</description><addressOffset>0x14</addressOffset></register><register><name>DUTY5</name><description>Duty cycle register 5</description><addressOffset>0x18</addressOffset></register><register><name>DUTY6</name><description>Duty cycle register 6</description><addressOffset>0x1C</addressOffset></register><register><name>DUTY7</name><description>Duty cycle register 7</description><addressOffset>0x20</addressOffset></register><register><name>DUTY8</name><description>Duty cycle register 8</description><addressOffset>0x24</addressOffset></register><register><name>DUTY9</name><description>Duty cycle register 9</description><addressOffset>0x28</addressOffset></register><register><name>DUTY10</name><description>Duty cycle register 10</description><addressOffset>0x2C</addressOffset></register><register><name>DUTY11</name><description>Duty cycle register 11</description><addressOffset>0x30</addressOffset></register><register><name>DUTY12</name><description>Duty cycle register 12</description><addressOffset>0x34</addressOffset></register><register><name>DUTY13</name><description>Duty cycle register 13</description><addressOffset>0x38</addressOffset></register><register><name>DUTY14</name><description>Duty cycle register 14</description><addressOffset>0x3C</addressOffset></register></registers></peripheral><!-- SLINK --><peripheral><name>SLINK</name><description>Stream link interface</description><groupName>SLINK</groupName><baseAddress>0xFFFFFEC0</baseAddress><interrupt><name>SLINK_RX_FIRQ</name><value>10</value></interrupt><interrupt><name>SLINK_TX_FIRQ</name><value>11</value></interrupt><addressBlock><offset>0</offset><size>0x40</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>SLINK_CTRL_RX_NUMx</name><access>read-only</access><bitRange>[3:0]</bitRange><description>Number of implemented RX links</description></field><field><name>SLINK_CTRL_TX_NUMx</name><access>read-only</access><bitRange>[7:4]</bitRange><description>Number of implemented TX links</description></field><field><name>SLINK_CTRL_RX_FIFO_Sx</name><access>read-only</access><bitRange>[11:8]</bitRange><description>log2(RX FIFO size)</description></field><field><name>SLINK_CTRL_TX_FIFO_Sx</name><access>read-only</access><bitRange>[15:12]</bitRange><description>log2(TX FIFO size)</description></field><field><name>SLINK_CTRL_EN</name><access>read-write</access><bitRange>[31:31]</bitRange><description>SLINK enable flag</description></field></fields></register><register><name>IRQ</name><description>Link interrupt configuration register</description><addressOffset>0x08</addressOffset><fields><field><name>SLINK_IRQ_RX_EN</name><bitRange>[7:0]</bitRange><description>RX link interrupt enable</description></field><field><name>SLINK_IRQ_RX_MODE</name><bitRange>[15:8]</bitRange><description>RX link interrupt mode</description></field><field><name>SLINK_IRQ_TX_EN</name><bitRange>[23:16]</bitRange><description>TX link interrupt enable</description></field><field><name>SLINK_IRQ_TX_MODE</name><bitRange>[31:24]</bitRange><description>TX link interrupt mode</description></field></fields></register><register><name>STATUS</name><description>Link status register</description><addressOffset>0x10</addressOffset><fields><field><name>SLINK_STATUS_RX_AVAIL</name><bitRange>[7:0]</bitRange><description>RX link n FIFO is NOT empty (data available)</description></field><field><name>SLINK_STATUS_TX_FREE</name><bitRange>[15:8]</bitRange><description>TX link n FIFO is NOT full (ready to send)</description></field><field><name>SLINK_STATUS_RX_HALF</name><bitRange>[23:16]</bitRange><description>RX link n FIFO fill level is >= half-full</description></field><field><name>SLINK_STATUS_TX_HALF</name><bitRange>[31:24]</bitRange><description>TX link 0 FIFO fill level is > half-full</description></field></fields></register><register><name>DATA0</name><description>Link 0 RTX data register</description><addressOffset>0x20</addressOffset></register><register><name>DATA1</name><description>Link 1 RTX data register</description><addressOffset>0x24</addressOffset></register><register><name>DATA2</name><description>Link 2 RTX data register</description><addressOffset>0x28</addressOffset></register><register><name>DATA3</name><description>Link 3 RTX data register</description><addressOffset>0x2C</addressOffset></register><register><name>DATA4</name><description>Link 4 RTX data register</description><addressOffset>0x30</addressOffset></register><register><name>DATA5</name><description>Link 5 RTX data register</description><addressOffset>0x34</addressOffset></register><register><name>DATA6</name><description>Link 6 RTX data register</description><addressOffset>0x38</addressOffset></register><register><name>DATA7</name><description>Link 7 RTX data register</description><addressOffset>0x3C</addressOffset></register></registers></peripheral><!-- XIP --><peripheral><name>XIP</name><description>Execute In Place Module</description><groupName>CIP</groupName><baseAddress>0xFFFFFF40</baseAddress><addressBlock><offset>0</offset><size>0x10</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>XIP_CTRL_EN</name><bitRange>[0:0]</bitRange><description>XIP module enable flag</description></field><field><name>XIP_CTRL_PRSC</name><bitRange>[3:1]</bitRange><description>SPI clock prescaler select</description></field><field><name>XIP_CTRL_CPOL</name><bitRange>[4:4]</bitRange><description>SPI clock (idle) polarity</description></field><field><name>XIP_CTRL_CPHA</name><bitRange>[5:5]</bitRange><description>SPI clock phase</description></field><field><name>XIP_CTRL_SPI_NBYTES</name><bitRange>[9:6]</bitRange><description>Number of bytes in SPI transmission</description></field><field><name>XIP_CTRL_XIP_EN</name><bitRange>[10:10]</bitRange><description>XIP mode enable</description></field><field><name>XIP_CTRL_XIP_ABYTES</name><bitRange>[12:11]</bitRange><description>Number of XIP address bytes (minus 1)</description></field><field><name>XIP_CTRL_RD_CMD</name><bitRange>[20:13]</bitRange><description>SPI flash read command</description></field><field><name>XIP_CTRL_XIP_PAGE</name><bitRange>[24:21]</bitRange><description>XIP memory page</description></field><field><name>XIP_CTRL_SPI_CSEN</name><bitRange>[25:25]</bitRange><description>SPI chip-select enable</description></field><field><name>XIP_CTRL_HIGHSPEED</name><bitRange>[26:26]</bitRange><description>SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)</description></field><field><name>XIP_CTRL_PHY_BUSY</name><bitRange>[30:30]</bitRange><access>read-only</access><description>SPI PHY busy</description></field><field><name>XIP_CTRL_XIP_BUSY</name><bitRange>[31:31]</bitRange><access>read-only</access><description>XIP access in progress</description></field></fields></register><register><name>DATA_LO</name><description>Direct SPI access - data register low</description><addressOffset>0x08</addressOffset></register><register><name>DATA_HI</name><description>Direct SPI access - data register high</description><addressOffset>0x0C</addressOffset></register></registers></peripheral><!-- GPTMR --><peripheral><name>GPTMR</name><description>General purpose timer</description><groupName>GPTMR</groupName><baseAddress>0xFFFFFF60</baseAddress><interrupt><name>GPTMR_FIRQ</name><value>12</value></interrupt><addressBlock><offset>0</offset><size>0x10</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>GPTMR_CTRL_EN</name><bitRange>[0:0]</bitRange><description>Timer enable flag</description></field><field><name>GPTMR_CTRL_PRSC</name><bitRange>[3:1]</bitRange><description>Clock prescaler select</description></field><field><name>GPTMR_CTRL_MODE</name><bitRange>[4:4]</bitRange><description>Timer mode: 0=single-shot mode, 1=continuous mode</description></field></fields></register><register><name>THRES</name><description>Threshold register</description><addressOffset>0x04</addressOffset></register><register><name>COUNT</name><description>Counter register</description><addressOffset>0x08</addressOffset></register></registers></peripheral><!-- BUSKEEPER --><peripheral><name>BUSKEEPER</name><description>Bus keeper</description><groupName>BUSKEEPER</groupName><baseAddress>0xFFFFFF7C</baseAddress><addressBlock><offset>0</offset><size>0x04</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>BUSKEEPER_ERR_TYPE</name><bitRange>[0:0]</bitRange><access>read-only</access><description>Bus error type: 0=device error, 1=access timeout</description></field><field><name>BUSKEEPER_ERR_FLAG</name><bitRange>[31:31]</bitRange><description>Sticky error flag, clears after read or write access</description></field></fields></register></registers></peripheral><!-- XIRQ --><peripheral><name>XIRQ</name><description>External interrupts controller</description><groupName>XIRQ</groupName><baseAddress>0xFFFFFF80</baseAddress><interrupt><name>XIRQ_FIRQ</name><value>8</value></interrupt><addressBlock><offset>0</offset><size>0x10</size><usage>registers</usage></addressBlock><registers><register><name>IER</name><description>IRQ input enable register</description><addressOffset>0x00</addressOffset></register><register><name>IPR</name><description>IRQ pending/ack/clear register</description><addressOffset>0x04</addressOffset></register><register><name>SCR</name><description>IRQ source register</description><addressOffset>0x08</addressOffset></register></registers></peripheral><!-- MTIME --><peripheral><name>MTIME</name><description>Machine timer</description><groupName>MTIME</groupName><baseAddress>0xFFFFFF90</baseAddress><addressBlock><offset>0</offset><size>0x10</size><usage>registers</usage></addressBlock><registers><register><name>TIME_LO</name><description>System time register - low</description><addressOffset>0x00</addressOffset></register><register><name>TIME_HI</name><description>System time register - high</description><addressOffset>0x04</addressOffset></register><register><name>TIMECMP_LO</name><description>Time compare register - low</description><addressOffset>0x08</addressOffset></register><register><name>TIMECMP_HI</name><description>Time compare register - high</description><addressOffset>0x0C</addressOffset></register></registers></peripheral><!-- UART0 --><peripheral><name>UART0</name><description>Primary universal asynchronous receiver and transmitter</description><groupName>UART0</groupName><baseAddress>0xFFFFFFA0</baseAddress><interrupt><name>UART0_RX_FIRQ</name><value>2</value></interrupt><interrupt><name>UART0_TX_FIRQ</name><value>3</value></interrupt><addressBlock><offset>0</offset><size>0x08</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>UART_CTRL_BAUD</name><bitRange>[11:0]</bitRange><description>Baud rate divisor</description></field><field><name>UART_CTRL_SIM_MODE</name><bitRange>[12:12]</bitRange><description>Simulation output override enable, for use in simulation only</description></field><field><name>UART_CTRL_RX_EMPTY</name><bitRange>[13:13]</bitRange><access>read-only</access><description>RX FIFO is empty</description></field><field><name>UART_CTRL_RX_HALF</name><bitRange>[14:14]</bitRange><access>read-only</access><description>RX FIFO is at least half-full</description></field><field><name>UART_CTRL_RX_FULL</name><bitRange>[15:15]</bitRange><access>read-only</access><description>RX FIFO is full</description></field><field><name>UART_CTRL_TX_EMPTY</name><bitRange>[16:16]</bitRange><access>read-only</access><description>TX FIFO is empty</description></field><field><name>UART_CTRL_TX_HALF</name><bitRange>[17:17]</bitRange><access>read-only</access><description>TX FIFO is at least half-full</description></field><field><name>UART_CTRL_TX_FULL</name><bitRange>[18:18]</bitRange><access>read-only</access><description>TX FIFO is full</description></field><field><name>UART_CTRL_RTS_EN</name><bitRange>[20:20]</bitRange><description>Enable hardware flow control: Assert RTS output if UART.RX is ready to receive</description></field><field><name>UART_CTRL_CTS_EN</name><bitRange>[21:21]</bitRange><description>Enable hardware flow control: UART.TX starts sending only if CTS input is asserted</description></field><field><name>UART_CTRL_PMODE0</name><bitRange>[22:22]</bitRange><description>Parity configuration (0=even; 1=odd)</description></field><field><name>UART_CTRL_PMODE1</name><bitRange>[23:23]</bitRange><description>Parity bit enabled when set</description></field><field><name>UART_CTRL_PRSC</name><bitRange>[26:24]</bitRange><description>Clock prescaler select</description></field><field><name>UART_CTRL_CTS</name><bitRange>[27:27]</bitRange><access>read-only</access><description>current state of CTS input</description></field><field><name>UART_CTRL_EN</name><bitRange>[28:28]</bitRange><description>UART enable flag</description></field><field><name>UART_CTRL_RX_IRQ</name><bitRange>[29:29]</bitRange><description>RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty</description></field><field><name>UART_CTRL_TX_IRQ</name><bitRange>[30:30]</bitRange><description>TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full</description></field><field><name>UART_CTRL_TX_BUSY</name><bitRange>[31:31]</bitRange><access>read-only</access><description>Transmitter is busy when set</description></field></fields></register><register><name>DATA</name><description>RX/TX data register</description><addressOffset>0x04</addressOffset><fields><field><name>UART_DATA</name><bitRange>[7:0]</bitRange><description>Receive/transmit data</description></field><field><name>UART_DATA_PERR</name><bitRange>[28:28]</bitRange><access>read-only</access><description>RX parity error detected when set</description></field><field><name>UART_DATA_FERR</name><bitRange>[29:29]</bitRange><access>read-only</access><description>RX frame error (no valid stop bit) detected when set</description></field><field><name>UART_DATA_OVERR</name><bitRange>[30:30]</bitRange><access>read-only</access><description>RX parity error detected when set</description></field><field><name>UART_DATA_AVAIL</name><bitRange>[31:31]</bitRange><access>read-only</access><description>RX data available when set</description></field></fields></register></registers></peripheral><!-- UART1 --><peripheral derivedFrom="UART0"><name>UART1</name><description>Secondary universal asynchronous receiver and transmitter</description><groupName>UART1</groupName><baseAddress>0xFFFFFFD0</baseAddress><interrupt><name>UART1_RX_FIRQ</name><value>4</value></interrupt><interrupt><name>UART1_TX_FIRQ</name><value>5</value></interrupt><addressBlock><offset>0</offset><size>0x08</size><usage>registers</usage></addressBlock></peripheral><!-- SPI --><peripheral><name>SPI</name><description>Serial peripheral interface controller</description><groupName>SPI</groupName><baseAddress>0xFFFFFFA8</baseAddress><interrupt><name>SPI_FIRQ</name><value>6</value></interrupt><addressBlock><offset>0</offset><size>0x08</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>SPI_CTRL_CS</name><bitRange>[7:0]</bitRange><description>Direct chip select line</description></field><field><name>SPI_CTRL_EN</name><bitRange>[8:8]</bitRange><description>SPI enable flag</description></field><field><name>SPI_CTRL_CPHA</name><bitRange>[9:9]</bitRange><description>Clock phase</description></field><field><name>SPI_CTRL_PRSC</name><bitRange>[12:10]</bitRange><description>Clock prescaler select</description></field><field><name>SPI_CTRL_SIZE</name><bitRange>[14:13]</bitRange><description>Data transfer size</description></field><field><name>SPI_CTRL_CPOL</name><bitRange>[15:15]</bitRange><description>Clock polarity</description></field><field><name>SPI_CTRL_HIGHSPEED</name><bitRange>[16:16]</bitRange><description>SPI high-speed mode enable (ignoring SPI_CTRL_PRSC)</description></field><field><name>SPI_CTRL_BUSY</name><bitRange>[31:31]</bitRange><access>read-only</access><description>SPI busy flag</description></field></fields></register><register><name>DATA</name><description>RX/TX data register</description><addressOffset>0x04</addressOffset></register></registers></peripheral><!-- TWI --><peripheral><name>TWI</name><description>Two-wire interface controller</description><groupName>SPI</groupName><baseAddress>0xFFFFFFB0</baseAddress><interrupt><name>TWI_FIRQ</name><value>7</value></interrupt><addressBlock><offset>0</offset><size>0x08</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>TWI_CTRL_EN</name><bitRange>[0:0]</bitRange><description>TWI enable flag</description></field><field><name>TWI_CTRL_START</name><bitRange>[1:1]</bitRange><description>Generate START condition, auto-clears</description></field><field><name>TWI_CTRL_STOP</name><bitRange>[2:2]</bitRange><description>Generate STOP condition, auto-clears</description></field><field><name>TWI_CTRL_PRSC</name><bitRange>[5:3]</bitRange><description>Clock prescaler select</description></field><field><name>TWI_CTRL_MACK</name><bitRange>[6:6]</bitRange><description>Generate ACK by controller for each transmission</description></field><field><name>TWI_CTRL_ACK</name><bitRange>[30:30]</bitRange><access>read-only</access><description>ACK received when set</description></field><field><name>TWI_CTRL_BUSY</name><bitRange>[31:31]</bitRange><access>read-only</access><description>Transfer in progress, busy flag</description></field></fields></register><register><name>DATA</name><description>RX/TX data register</description><addressOffset>0x04</addressOffset><fields><field><name>TWI_DATA</name><bitRange>[7:0]</bitRange><description>RX/TX data</description></field></fields></register></registers></peripheral><!-- TRNG --><peripheral><name>TRNG</name><description>True random number generator</description><groupName>TRNG</groupName><baseAddress>0xFFFFFFB8</baseAddress><addressBlock><offset>0</offset><size>0x04</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control and data register</description><addressOffset>0x00</addressOffset><fields><field><name>TRNG_CTRL_DATA</name><bitRange>[7:0]</bitRange><access>read-only</access><description>Random data</description></field><field><name>TRNG_CTRL_EN</name><bitRange>[30:30]</bitRange><description>TRNG enable flag</description></field><field><name>TRNG_CTRL_VALID</name><bitRange>[31:31]</bitRange><access>read-only</access><description>Random data output valid</description></field></fields></register></registers></peripheral><!-- WDT --><peripheral><name>WDT</name><description>Watchdog timer</description><groupName>WDT</groupName><baseAddress>0xFFFFFFBC</baseAddress><interrupt><name>WDT_FIRQ</name><value>0</value></interrupt><addressBlock><offset>0</offset><size>0x04</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>WDT_CTRL_EN</name><bitRange>[0:0]</bitRange><description>WDT enable flag</description></field><field><name>WDT_CTRL_CLK_SEL</name><bitRange>[3:1]</bitRange><description>Clock prescaler select</description></field><field><name>WDT_CTRL_MODE</name><bitRange>[4:4]</bitRange><description>Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset</description></field><field><name>WDT_CTRL_RCAUSE</name><bitRange>[5:5]</bitRange><access>read-only</access><description>Cause of last system reset: 0=external reset, 1=watchdog</description></field><field><name>WDT_CTRL_RESET</name><bitRange>[6:6]</bitRange><description>Reset WDT counter when set, auto-clears</description></field><field><name>WDT_CTRL_FORCE</name><bitRange>[7:7]</bitRange><description>Force WDT action, auto-clears</description></field><field><name>WDT_CTRL_LOCK</name><bitRange>[8:8]</bitRange><description>Lock write access to control register, clears on reset (HW or WDT) only</description></field><field><name>WDT_CTRL_DBEN</name><bitRange>[9:9]</bitRange><description>Allow WDT to continue operation even when in debug mode</description></field><field><name>WDT_CTRL_HALF</name><bitRange>[10:10]</bitRange><access>read-only</access><description>Set if at least half of the max. timeout counter value has been reached</description></field></fields></register></registers></peripheral><!-- GPIO --><peripheral><name>GPIO</name><description>General purpose input/output port</description><groupName>GPIO</groupName><baseAddress>0xFFFFFFc0</baseAddress><addressBlock><offset>0</offset><size>0x10</size><usage>registers</usage></addressBlock><registers><register><name>INPUT_LO</name><description>Parallel input register - low</description><addressOffset>0x00</addressOffset><access>read-only</access></register><register><name>INPUT_HI</name><description>Parallel input register - high</description><addressOffset>0x04</addressOffset><access>read-only</access></register><register><name>OUTPUT_LO</name><description>Parallel output register - low</description><addressOffset>0x08</addressOffset></register><register><name>OUTPUT_HI</name><description>Parallel output register - high</description><addressOffset>0x0C</addressOffset></register></registers></peripheral><!-- NEOLED --><peripheral><name>NEOLED</name><description>Smart LED hardware interface</description><groupName>NEOLED</groupName><baseAddress>0xFFFFFFD8</baseAddress><interrupt><name>NEOLED_FIRQ</name><value>9</value></interrupt><addressBlock><offset>0</offset><size>0x08</size><usage>registers</usage></addressBlock><registers><register><name>CTRL</name><description>Control register</description><addressOffset>0x00</addressOffset><fields><field><name>NEOLED_CTRL_EN</name><bitRange>[0:0]</bitRange><description>NEOLED enable flag</description></field><field><name>NEOLED_CTRL_MODE</name><bitRange>[1:1]</bitRange><description>TX mode (0=24-bit, 1=32-bit)</description></field><field><name>NEOLED_CTRL_STROBE</name><bitRange>[2:2]</bitRange><description>Strobe (0=send normal data, 1=send RESET command on data write)</description></field><field><name>NEOLED_CTRL_PRSC</name><bitRange>[5:3]</bitRange><description>Clock prescaler select</description></field><field><name>NEOLED_CTRL_BUFS</name><bitRange>[9:6]</bitRange><access>read-only</access><description>log2(tx buffer size)</description></field><field><name>NEOLED_CTRL_T_TOT</name><bitRange>[14:10]</bitRange><description>pulse-clock ticks per total period bit</description></field><field><name>NEOLED_CTRL_T_ZERO_H</name><bitRange>[19:15]</bitRange><description>pulse-clock ticks per ZERO high-time</description></field><field><name>NEOLED_CTRL_T_ONE_H</name><bitRange>[24:20]</bitRange><description>pulse-clock ticks per ONE high-time</description></field><field><name>NEOLED_CTRL_IRQ_CONF</name><bitRange>[27:27]</bitRange><description>TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty</description></field><field><name>NEOLED_CTRL_TX_EMPTY</name><bitRange>[28:28]</bitRange><access>read-only</access><description>TX FIFO is empty</description></field><field><name>NEOLED_CTRL_TX_HALF</name><bitRange>[29:29]</bitRange><access>read-only</access><description>TX FIFO is at least half-full</description></field><field><name>NEOLED_CTRL_TX_FULL</name><bitRange>[30:30]</bitRange><access>read-only</access><description>TX FIFO is full</description></field><field><name>NEOLED_CTRL_TX_BUSY</name><bitRange>[31:31]</bitRange><access>read-only</access><description>busy flag</description></field></fields></register><register><name>DATA</name><description>Data register</description><addressOffset>0x04</addressOffset></register></registers></peripheral><!-- SYSINFO --><peripheral><name>SYSINFO</name><description>System configuration information memory</description><groupName>SYSINFO</groupName><baseAddress>0xFFFFFFE0</baseAddress><addressBlock><offset>0</offset><size>0x20</size><usage>registers</usage></addressBlock><registers><register><name>CLK</name><description>Clock speed in Hz</description><addressOffset>0x00</addressOffset><access>read-only</access></register><register><name>SOC</name><description>SoC features</description><addressOffset>0x08</addressOffset><access>read-only</access><fields><field><name>SYSINFO_SOC_BOOTLOADER</name><bitRange>[0:0]</bitRange><description>Bootloader implemented</description></field><field><name>SYSINFO_SOC_MEM_EXT</name><bitRange>[1:1]</bitRange><description>External bus interface implemented</description></field><field><name>SYSINFO_SOC_MEM_INT_IMEM</name><bitRange>[2:2]</bitRange><description>Processor-internal instruction memory implemented</description></field><field><name>SYSINFO_SOC_MEM_INT_DMEM</name><bitRange>[3:3]</bitRange><description>Processor-internal data memory implemented</description></field><field><name>SYSINFO_SOC_MEM_EXT_ENDIAN</name><bitRange>[4:4]</bitRange><description>External bus interface uses BIG-endian byte-order</description></field><field><name>SYSINFO_SOC_ICACHE</name><bitRange>[5:5]</bitRange><description>Processor-internal instruction cache implemented</description></field><field><name>SYSINFO_SOC_IS_SIM</name><bitRange>[13:13]</bitRange><description>Set if processor is being simulated</description></field><field><name>SYSINFO_SOC_OCD</name><bitRange>[14:14]</bitRange><description>On-chip debugger implemented</description></field><field><name>SYSINFO_SOC_HW_RESET</name><bitRange>[15:15]</bitRange><description>Dedicated hardware reset of core registers implemented</description></field><field><name>SYSINFO_SOC_IO_GPIO</name><bitRange>[16:16]</bitRange><description>General purpose input/output port unit implemented</description></field><field><name>SYSINFO_SOC_IO_MTIME</name><bitRange>[17:17]</bitRange><description>Machine system timer implemented</description></field><field><name>SYSINFO_SOC_IO_UART0</name><bitRange>[18:18]</bitRange><description>Primary universal asynchronous receiver/transmitter 0 implemented</description></field><field><name>SYSINFO_SOC_IO_SPI</name><bitRange>[19:19]</bitRange><description>Serial peripheral interface implemented</description></field><field><name>SYSINFO_SOC_IO_TWI</name><bitRange>[20:20]</bitRange><description>Two-wire interface implemented</description></field><field><name>SYSINFO_SOC_IO_PWM</name><bitRange>[21:21]</bitRange><description>Pulse-width modulation unit implemented</description></field><field><name>SYSINFO_SOC_IO_WDT</name><bitRange>[22:22]</bitRange><description>Watchdog timer implemented</description></field><field><name>SYSINFO_SOC_IO_CFS</name><bitRange>[23:23]</bitRange><description>Custom functions subsystem implemented</description></field><field><name>SYSINFO_SOC_IO_TRNG</name><bitRange>[24:24]</bitRange><description>True random number generator implemented</description></field><field><name>SYSINFO_SOC_IO_SLINK</name><bitRange>[25:25]</bitRange><description>Stream link interface implemented</description></field><field><name>SYSINFO_SOC_IO_UART1</name><bitRange>[26:26]</bitRange><description>Secondary universal asynchronous receiver/transmitter 1 implemented</description></field><field><name>SYSINFO_SOC_IO_NEOLED</name><bitRange>[27:27]</bitRange><description>NeoPixel-compatible smart LED interface implemented</description></field><field><name>SYSINFO_SOC_IO_XIRQ</name><bitRange>[28:28]</bitRange><description>External interrupt controller implemented</description></field><field><name>SYSINFO_SOC_IO_GPTMR</name><bitRange>[29:29]</bitRange><description>General purpose timer implemented</description></field><field><name>SYSINFO_SOC_IO_XIP</name><bitRange>[30:30]</bitRange><description>Execute in place module implemented</description></field></fields></register><register><name>CACHE</name><description>Cache configuration</description><addressOffset>0x0C</addressOffset><access>read-only</access><fields><field><name>SYSINFO_CACHE_IC_BLOCK_SIZE</name><bitRange>[3:0]</bitRange><description>i-cache: log2(Block size in bytes)</description></field><field><name>SYSINFO_CACHE_IC_NUM_BLOCKS</name><bitRange>[7:4]</bitRange><description>i-cache: log2(Number of cache blocks/pages/lines)</description></field><field><name>SYSINFO_CACHE_IC_ASSOCIATIVITY</name><bitRange>[11:8]</bitRange><description>i-cache: log2(associativity)</description></field><field><name>SYSINFO_CACHE_IC_REPLACEMENT</name><bitRange>[15:12]</bitRange><description>i-cache: replacement policy (0001 = LRU if associativity > 0)</description></field></fields></register><register><name>ISPACE_BASE</name><description>Instruction memory address space base address</description><addressOffset>0x10</addressOffset><access>read-only</access></register><register><name>DSPACE_BASE</name><description>Data memory address space base address</description><addressOffset>0x14</addressOffset><access>read-only</access></register><register><name>IMEM_SIZE</name><description>Internal instruction memory (IMEM) size in bytes</description><addressOffset>0x18</addressOffset><access>read-only</access></register><register><name>DMEM_SIZE</name><description>Internal data memory (DMEM) size in bytes</description><addressOffset>0x1C</addressOffset><access>read-only</access></register></registers></peripheral></peripherals></device>