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[/] [neural_net_perceptron/] [trunk/] [sim/] [04_tb_avm_instruction_gen_v05_public.do] - Rev 15
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# generate foreign module declarationonerror {resume}# create libraryif [file exists {./work}] {vdel -all {./work}}vlib {./work}## Add logical mapping >work< to the local design simulation library#vmap work {./work}#pwd## Open debugging windows#quietly view *## Start and run simulation#set StdArithNoWarnings 1vcom -work "work" -nologo -2008 -F 03_file_list.txtvcom -work "work" -nologo -93 ../tb/vhdl/tb_avm_instruction_gen_v05_public.vhdvsim -no_autoacc -L work -coverage -voptargs="+cover=bcesfx" -l transcript.txt -i -multisource_delay latest -t ns +typdelays work.tb_avm_instruction_gen_v05_public(testbench)assertion activeassertion profile onassertion report -verboseconfigure wave -namecolwidth 450#configure wave -valuecolwidth 145configure wave -valuecolwidth 120configure wave -justifyvalue leftconfigure wave -signalnamewidth 0configure wave -snapdistance 10configure wave -datasetprefix 0configure wave -rowmargin 4configure wave -childrowmargin 2configure wave -gridoffset 0configure wave -gridperiod 1configure wave -griddelta 40configure wave -timeline 0configure wave -timelineunits psupdate# View the results.#if {![batch_mode]} {quietly add wave -divider TB_TOP_LEVELquietly add wave -expand /stream01quietly add wave -expand /stream02quietly add wave -group TB_TOP_LEVEL /*quietly add wave -divider TOP_LEVELquietly add wave -group TOP_LEVEL /u_0/*quietly add wave -divider PERCEPTRONquietly add wave -group PERCEPTRON /u_0/u_0/*quietly add wave -divider WISHBONEquietly add wave -group WISHBONE /u_0/u_0/u_14/*quietly add wave -divider FOR_LOOP_Iquietly add wave -group FOR_LOOP_I /u_0/u_0/u_2/*quietly add wave -divider FOR_LOOP_Jquietly add wave -group FOR_LOOP_J /u_0/u_0/u_1/*quietly add wave -divider CAL_Yquietly add wave -group CAL_Y /u_0/u_0/u_0/*quietly add wave -divider CAL_Wquietly add wave -group CAL_W /u_0/u_0/u_8/*quietly add wave -divider INITquietly add wave -group INIT /u_0/u_0/u_9/*quietly add wave -divider TESTquietly add wave -group TEST /u_0/u_0/u_10/*quietly add wave -divider READ_WRITEquietly add wave -group READ_WRITE /u_0/u_0/u_11/*quietly add wave -divider TRAININGquietly add wave -group TRAINING /u_0/u_0/u_12/*quietly add wave -divider LATENCYquietly add wave -group LATENCY /u_0/u_0/u_13/*quietly add wave -divider S-MEMORYquietly add wave -group S-MEMORY /u_0/u_1/u_0/*quietly add wave -divider T-MEMORYquietly add wave -group T-MEMORY /u_0/u_1/u_1/*quietly add wave -divider Y-MEMORYquietly add wave -group Y-MEMORY /u_0/u_1/u_2/*quietly add wave -divider BIAS-MEMORYquietly add wave -group BIAS-MEMORY /u_0/u_1/u_3/*quietly add wave -divider W-MEMORYquietly add wave -group W-MEMORY /u_0/u_1/u_4/*#quietly add wave -r /*#}run -allquietly wave zoomfullupdate#U_0/U_0/U_0coverage exclude -du p0300_m00022_s_v02_cal_y_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00 \S09->S00 \S10->S00 \S11->S00 \S12->S00 \S13->S00 \S14->S00 \S15->S00 \S16->S00#U_0/U_0/U_1coverage exclude -du p0300_m00034_s_v01_for_loop_memwj_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00#U_0/U_0/U_2coverage exclude -du p0300_m00033_s_v01_for_loop_memwi_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00#U_0/U_0/U_8coverage exclude -du p0300_m00023_s_v02_cal_w_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00 \S09->S00 \S10->S00 \S11->S00 \S12->S00 \S13->S00 \S14->S00 \S15->S00 \S16->S00#U_0/U_0/U_9coverage exclude -du p0300_m00025_s_v02_init_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00#U_0/U_0/U_10coverage exclude -du p0300_m00024_s_v02_test_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00 \S09->S00 \S10->S00 \S11->S00 \S12->S00 \S13->S00 \S14->S00 \S15->S00 \S16->S00 \S17->S00#U_0/U_0/U_11coverage exclude -du p0300_m00026_s_v02_rd_wr_fsm -ftrans current_state S01->S00 \S02->S00 \S12->S00 \S22->S00 \S32->S00 \S42->S00 \S03->S00 \S04->S00#U_0/U_0/U_12coverage exclude -du p0300_m00027_s_v01_train_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00 \S09->S00 \S10->S00 \S11->S00 \S12->S00 \S13->S00#U_0/U_0/U_13coverage exclude -du p0300_m00028_s_v02_latency_fsm -ftrans current_state S01->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00 \S09->S00 \S10->S00 \S11->S00 \SRDY->S00 \SERR->S00#U_0/U_0/U_14coverage exclude -du p0300_m00021_s_v03_wishbone_fsm -ftrans current_state S01->S00 \S01a->S00 \S02->S00 \S03->S00 \S04->S00 \S05->S00 \S06->S00 \S07->S00 \S08->S00 \S09->S00 \S10->S00 \S11->S00 \S12->S00 \S13->S00 \S14->S00 \S15->S00 \S16->S00 \S17->S00 \S18->S00 \S19->S00 \S20->S00 \S21->S00 \S22->S00 \S23->S00 \S24->S00 \S25->S00 \S26->S00 \S27->S00 \S28->S00 \S29->S00 \S30->S00 \S31->S00 \S32->S00 \S33->S00 \S34->S00 \S35->S00 \S36->S00 \S37->S00 \S38->S00 \S39->S00 \S40->S00 \S41->S00 \S42->S00 \S43->S00 \S44->S00 \S45->S00 \S46->S00 \S47->S00 \S48->S00