Subversion Repositories next186_soc_pc

                            Datasheet  
Generated by mig Version 3.6.1
Sat Jan 28 16:23:16 2012

CORE Generator Options:
   FPGA Family                : spartan3a
   FPGA Part                  : xc3s700an-fgg484
   Speed Grade                : -4
   Synthesis Tool             : ISE
   HDL                        : verilog

MIG Output Options:
   Component Name              : ddr
   No of Controllers           : 1
   Selected Compatible Devices : --
   Hardware Test Bench           : disabled
    
Controller Options :
   Frequency                  : 133.00 MHz(7519 ps)
   Write Pipe Stages          : 4
   Memory                     : DDR2_SDRAM
   Memory Type                : Components
   Memory Part                : MT47H32M16XX-3
   Equivalent Part(s)         : MT47H32M16BN-3;MT47H32M16CC-3;MT47H32M16FN-3;MT47H32M16GC-3
   Row Address                : 13
   Column Address             : 10
   Bank Address               : 2
   Data Width                 : 16
   Data Mask                  : enabled

Memory Options :
   Burst Length                       : 4(010)
   Burst Type                         : sequential(0)
   CAS Latency                        : 3(011)
   DLL Reset                          : yes(1)
   Mode                               : normal(0)
   Write Recovery                     : 3(010)

   DQS# Enable                        : Enable(0)
   DLL Enable                         : Enable-Normal(0)
   OCD Operation                      : OCD Exit(000)
   Output Drive Strength              : Fullstrength(0)
   Outputs                            : Enable(0)
   RDQS Enable                        : Disable(0)
   RTT (nominal) - ODT                : RTT Disabled(00)

FPGA Options :
   DCM option                           : disabled
   SSTL Class for Address/Control       : Class II
   SSTL Class for Data                  : Class II
   Debug Signals for Memory Controller  : Disable
   System Clock                         : Single-Ended

Reserved Pins :
   --

    Banks for Data           : 3
    WASSO for Data banks     : 69, 
    WASSO for all banks      : Bank 0 - 0
                               Bank 1 - 0
                               Bank 2 - 0
                               Bank 3 - 69
                               Bank 4 - 0
                               Bank 5 - 0
                               Bank 6 - 0
                               Bank 7 - 0
    Data bits                : 16
    Banks for Address/Control: 3
    Banks for System Control : 3
    Banks for System Clock   : 


    ********************************************