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-- Copyright (C) 2010 Arif Endro Nugroho
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c6b is
  port (
  cnt : out bit_vector (  5 downto 0);
  clk : in  bit;
  rst : in  bit
  );
end c6b;
 
architecture phy of c6b is
  signal sum : bit_vector (  5 downto 0); -- sum
  signal cr  : bit_vector (  5 downto 0); -- carry
  begin
    cr(0)            <= '0'; -- LSB always zero
    cr(5 downto 1) <= ( ((sum(4 downto 0) and B"00001") or (sum(4 downto 0) and cr(4 downto 0))) or (B"00001" and cr(4 downto 0)) );
    process (clk)
    begin
      if (clk = '1' and clk'event) then
        if (rst = '1') then
          sum <= B"000000";
        else
          sum <= ((sum xor B"000001") xor cr); -- sum = ((addend xor augend) xor carry)
        end if;
      end if;
    end process;
    cnt <= sum;
end phy;