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-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity xtime_4 is
port (
  x4i : in  bit_vector (07 downto 00);
  x4o : out bit_vector (07 downto 00)
);
end xtime_4;
 
architecture phy of xtime_4 is
begin
	x4o <= (  x4i(05) & x4i(04) & ( x4i(03) xor x4i(07) ) & ( x4i(02) xor x4i(07) xor x4i(06) ) & ( x4i(01) xor x4i(06) ) & ( x4i(00) xor x4i(07) ) & ( x4i(07) xor x4i(06) ) & x4i(06) );
end phy;