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https://opencores.org/ocsvn/nlprg/nlprg/trunk
Subversion Repositories nlprg
[/] [nlprg/] [trunk/] [tb/] [wave/] [prng8_tb.vcd] - Rev 2
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$dateSat Apr 18 17:08:32 2020$end$versionIcarus Verilog$end$timescale1s$end$scope module prng8_tb $end$var wire 1 ! prng_start_state $end$var wire 1 " o7 $end$var wire 1 # o6 $end$var wire 1 $ o5 $end$var wire 1 % o4 $end$var wire 1 & o3 $end$var wire 1 ' o2 $end$var wire 1 ( o1 $end$var wire 1 ) o0 $end$var wire 8 * o [7:0] $end$var wire 1 + cnt_start_state $end$var reg 1 , ck $end$var reg 8 - cnt [7:0] $end$var reg 1 . endsim $end$var reg 1 / pass $end$var reg 1 0 rst $end$var reg 1 1 rst_d0 $end$var reg 1 2 rst_d1 $end$var integer 32 3 f [31:0] $end$scope module nlprg8_u $end$var wire 1 , ck $end$var wire 1 ) o0 $end$var wire 1 ( o1 $end$var wire 1 ' o2 $end$var wire 1 & o3 $end$var wire 1 % o4 $end$var wire 1 $ o5 $end$var wire 1 # o6 $end$var wire 1 " o7 $end$var wire 1 0 rst $end$var wire 1 4 s0 $end$var wire 1 5 s1 $end$var wire 1 6 s2 $end$var wire 1 7 s3 $end$var wire 1 8 o7_temp $end$var wire 1 9 o6_temp $end$var wire 1 : o5_temp $end$var wire 1 ; o4_temp $end$var wire 1 < o3_temp $end$var wire 1 = o2_temp $end$var wire 1 > o1_temp $end$var wire 1 ? o0_temp $end$scope module dff0 $end$var wire 1 , ck $end$var wire 1 4 d $end$var wire 1 0 rst $end$var wire 1 ? q $end$var reg 1 ? state $end$upscope $end$scope module dff1 $end$var wire 1 , ck $end$var wire 1 5 d $end$var wire 1 0 rst $end$var wire 1 = q $end$var reg 1 = state $end$upscope $end$scope module dff2 $end$var wire 1 , ck $end$var wire 1 6 d $end$var wire 1 0 rst $end$var wire 1 > q $end$var reg 1 > state $end$upscope $end$scope module dff3 $end$var wire 1 , ck $end$var wire 1 7 d $end$var wire 1 0 rst $end$var wire 1 < q $end$var reg 1 < state $end$upscope $end$scope module dff4 $end$var wire 1 , ck $end$var wire 1 0 rst $end$var wire 1 : q $end$var wire 1 ; d $end$var reg 1 : state $end$upscope $end$scope module dff5 $end$var wire 1 , ck $end$var wire 1 < d $end$var wire 1 0 rst $end$var wire 1 ; q $end$var reg 1 ; state $end$upscope $end$scope module dff6 $end$var wire 1 , ck $end$var wire 1 : d $end$var wire 1 0 rst $end$var wire 1 9 q $end$var reg 1 9 state $end$upscope $end$scope module dff7 $end$var wire 1 , ck $end$var wire 1 9 d $end$var wire 1 0 rst $end$var wire 1 8 q $end$var reg 1 8 state $end$upscope $end$upscope $end$scope begin cnt_process $end$upscope $end$scope begin display_process $end$upscope $end$scope begin end_sim_process $end$upscope $end$scope begin reset_delay_process $end$upscope $end$upscope $end$enddefinitions $end#0$dumpvars0?0>0=0<0;0:090807060514b10000000000000000000000000000011 3x2x110x/x.bx -x,x+b0 *0)0(0'0&0%0$0#0"1!$end#500#100/0.12111+b0 -10#1516010+b1 -0!b10000000 *1)1?1,00#200,#251502b10 -b11000000 *1(1>1,#300,#3517b11 -b11100000 *1'1=1,#400,#450504b100 -b11110000 *1&1<1,#500,#55150607b101 -0)0?0'0=b1011000 *1%1;1,#600,#65161514b110 -1$1:0&0<0(0>b101100 *1'1=1,#700,#75041615b111 -1)1?1(1>0%0;b11100110 *1#191,#800,#85141716b1000 -1"180$0:b1100011 *0)0?1,#900,#95051614b1001 -1)1?1&1<b11110001 *0#091,#1000,#105150407b1010 -0"081%1;b11011000 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