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!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/!_TAG_PROGRAM_NAME Exuberant Ctags //!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/!_TAG_PROGRAM_VERSION 5.6 //BUSY define.h 7;" dCACHE router.h /^typedef struct CACHE{$/;" sCC Makefile /^CC = g++$/;" mCFLAGS Makefile /^CFLAGS = -Wall -g $/;" mCORE packet_header.h 19;" dCORE_ADDRESS router.h 15;" dCORE_H core.h 2;" dDEFINE_H define.h 5;" dDELAY define.h 12;" dEAST packet_header.h 21;" dEAST_ADDRESS router.h 17;" dEMPTY define.h 10;" dFAIL define.h 16;" dFIFO1 core.h 10;" dFIFO2 core.h 11;" dFIFO3 core.h 12;" dFIFO_DEEP define.h 13;" dFIFO_H fifo.h 2;" dFIFO_STAGE define.h 14;" dFIFO_TB_H top.h 19;" dFLIT_DST packet_header.h 13;" dFLIT_SIZE packet_header.h 11;" dFLIT_TYPE packet_header.h 12;" dFULL define.h 9;" dHEAD_FLIT packet_header.h /^typedef struct HEAD_FLIT{$/;" sIDLE define.h 8;" dINC_DIRS Makefile /^INC_DIRS = -I$(SYSTEMC)\/include $/;" mLIBS Makefile /^LIBS = -lsystemc$/;" mLIB_DIRS Makefile /^LIB_DIRS = -L$(SYSTEMC)\/lib-linux$/;" mNOC_INFO define.h /^typedef struct NOC_INFO{$/;" sNORTH packet_header.h 22;" dNORTH_ADDRESS router.h 18;" dOBJECTS Makefile /^OBJECTS = fifo.o \\$/;" mPACKET_HEADER_H packet_header.h 2;" dPKT_SIZE packet_header.h 14;" dRE router.h 13;" dREAD_ADDRESS router.h 22;" dROUTER_H router.h 2;" dSC_CTOR core.h /^ SC_CTOR(core){$/;" f class:coreSC_CTOR fifo.h /^ SC_CTOR(virtual_fifo):fifo(FIFO_DEEP), fifo1(FIFO_DEEP), fifo2(FIFO_DEEP){$/;" f class:virtual_fifoSC_CTOR tile.h /^ SC_CTOR(tile){$/;" f class:tileSOUTH packet_header.h 23;" dSOUTH_ADDRESS router.h 19;" dSUCCEED define.h 17;" dSYSTEMC Makefile /^SYSTEMC = \/usr\/local\/systemc\/systemc-2.2.0$/;" mTARGET Makefile /^TARGET = onoc$/;" mTILE_TB_H tile.h 19;" dWE router.h 12;" dWEST packet_header.h 20;" dWEST_ADDRESS router.h 16;" dWRITE_ADDRESS router.h 21;" dac core.h /^ sc_uint<8> ac; \/\/address counter.$/;" m class:corebody_filt packet_header.h /^typedef struct body_filt{$/;" sc_data_in router.h /^ sc_in<bool> c_data_in; \/\/core input data port.$/;" m class:routerc_data_out router.h /^ sc_out<bool> c_data_out; \/\/core output data port.$/;" m class:routerc_empty router.h /^ sc_in<sc_uint<3> > c_empty; \/\/State of FIFO is full.$/;" m class:routerc_fifo_to_router_sel router.h /^ sc_out<sc_uint<2> > c_fifo_to_router_sel; \/\/north select signal.$/;" m class:routerc_full router.h /^ sc_in<sc_uint<3> > c_full; \/\/State of FIFO is empty.$/;" m class:routerc_raddress router.h /^ sc_uint<8> c_raddress;$/;" m class:routerc_read_en router.h /^ sc_event c_read_en;$/;" m class:routerc_read_n router.h /^ sc_out<bool> c_read_n; \/\/core input data control pin.$/;" m class:routerc_receive_data router.cc /^void router :: c_receive_data(){$/;" f class:routerc_router_to_fifo_sel router.h /^ sc_out<sc_uint<2> > c_router_to_fifo_sel; \/\/north select signal.$/;" m class:routerc_transfer_data router.cc /^void router :: c_transfer_data(){$/;" f class:routerc_waddress router.h /^ sc_uint<8> c_waddress;$/;" m class:routerc_write_en router.h /^ sc_event c_write_en;$/;" m class:routerc_write_n router.h /^ sc_out<bool> c_write_n; \/\/core output data control pin.$/;" m class:routercache router.h /^ CACHE cache[50]; \/\/MSB 2bit: flag space, rest 16bits: data space.$/;" m class:routerclk core.h /^ sc_in<bool> clk; \/\/input clock signal.$/;" m class:coreclk router.h /^ sc_in<bool> clk;$/;" m class:routerclk tile.h /^ sc_in<bool> clk;$/;" m class:tileclk top.h /^ sc_in<bool> clk;$/;" m class:topcolumn_num define.h /^ unsigned int column_num;$/;" m struct:NOC_INFOconn_type packet_header.h /^ unsigned conn_type : 1; \/\/'1' is optical interconnects and '0' is electrical interconnects.$/;" m struct:HEAD_FLITcore core.h /^class core : public sc_module{$/;" ccore_empty tile.h /^ sc_signal<sc_uint<3> > core_empty; \/\/State of FIFO is full.$/;" m class:tilecore_full tile.h /^ sc_signal<sc_uint<3> > core_full; \/\/State of FIFO is empty.$/;" m class:tilecore_handle core.cc /^void core :: core_handle()$/;" f class:corecore_to_fifo_read_n tile.h /^ sc_signal<bool> core_to_fifo_read_n; \/\/Input data control pin.$/;" m class:tilecore_to_fifo_sel core.h /^ sc_out<sc_uint<2> > core_to_fifo_sel; \/\/fifo select signal when transfer data. $/;" m class:corecore_to_fifo_write_n tile.h /^ sc_signal<bool> core_to_fifo_write_n; \/\/Output data control pin a.$/;" m class:tilecore_to_router_fifo tile.h /^ virtual_fifo *core_to_router_fifo;$/;" m class:tilect router.h /^ unsigned ct : 1; \/\/Complete flag.$/;" m struct:CACHEdata packet_header.h /^ unsigned data : 15;$/;" m struct:body_filtdata packet_header.h /^ unsigned short *data;$/;" m struct:packetdata router.h /^ unsigned data : 16; \/\/Data.$/;" m struct:CACHEdata_core_to_fifo tile.h /^ sc_signal<bool> data_core_to_fifo; \/\/transfer data from core to fifo.$/;" m class:tiledata_fifo_to_core tile.h /^ sc_signal<bool> data_fifo_to_core; \/\/transfer data from fifo to core.$/;" m class:tiledata_fifo_to_router tile.h /^ sc_signal<bool> data_fifo_to_router; \/\/transfer data from fifo to router.$/;" m class:tiledata_in core.h /^ sc_in<bool> data_in; \/\/core output data port.$/;" m class:coredata_in fifo.h /^ sc_in<bool> data_in; \/\/Input data port.$/;" m class:virtual_fifodata_in top.h /^ sc_signal<bool> data_in; \/\/Input data port.$/;" m class:topdata_out core.h /^ sc_out<bool> data_out; \/\/core input data port.$/;" m class:coredata_out fifo.h /^ sc_out<bool> data_out; \/\/Output data port.$/;" m class:virtual_fifodata_out top.h /^ sc_signal<bool> data_out; \/\/Output data port.$/;" m class:topdata_router_to_fifo tile.h /^ sc_signal<bool> data_router_to_fifo; \/\/transfer data from router to fifo.$/;" m class:tiledr router.h /^ unsigned dr : 3; \/\/Direction.$/;" m struct:CACHEdst_addr packet_header.h /^ unsigned dst_addr : 6; \/\/Destination address 2^6 = 64 address,so that is 64 tiles.$/;" m struct:HEAD_FLITe_data_in router.h /^ sc_in<bool> e_data_in; \/\/east input data port.$/;" m class:routere_data_in tile.h /^ sc_signal<bool> e_data_in;$/;" m class:tilee_data_out router.h /^ sc_out<bool> e_data_out; \/\/east output data port.$/;" m class:routere_data_out tile.h /^ sc_signal<bool> e_data_out;$/;" m class:tilee_empty router.h /^ sc_in<sc_uint<3> > e_empty; \/\/State of FIFO is full.$/;" m class:routere_empty tile.h /^ sc_signal<sc_uint<3> > e_empty; \/\/State of FIFO is full.$/;" m class:tilee_fifo_to_router_sel router.h /^ sc_out<sc_uint<2> > e_fifo_to_router_sel; \/\/east select signal.$/;" m class:routere_fifo_to_router_sel tile.h /^ sc_signal<sc_uint<2> > e_fifo_to_router_sel; \/\/west select signal.$/;" m class:tilee_full router.h /^ sc_in<sc_uint<3> > e_full; \/\/State of FIFO is empty.$/;" m class:routere_full tile.h /^ sc_signal<sc_uint<3> > e_full; \/\/State of FIFO is empty.$/;" m class:tilee_raddress router.h /^ sc_uint<8> e_raddress;$/;" m class:routere_read_en router.h /^ sc_event e_read_en;$/;" m class:routere_read_n router.h /^ sc_out<bool> e_read_n; \/\/right input data control pin.$/;" m class:routere_read_n tile.h /^ sc_signal<bool> e_read_n; \/\/left input data control pin.$/;" m class:tilee_receive_data router.cc /^void router :: e_receive_data(){$/;" f class:routere_router_to_fifo_sel router.h /^ sc_out<sc_uint<2> > e_router_to_fifo_sel; \/\/east select signal.$/;" m class:routere_router_to_fifo_sel tile.h /^ sc_signal<sc_uint<2> > e_router_to_fifo_sel; \/\/west select signal.$/;" m class:tilee_transfer_data router.cc /^void router :: e_transfer_data(){$/;" f class:routere_waddress router.h /^ sc_uint<8> e_waddress;$/;" m class:routere_write_en router.h /^ sc_event e_write_en;$/;" m class:routere_write_n router.h /^ sc_out<bool> e_write_n; \/\/right output data control pin.$/;" m class:routere_write_n tile.h /^ sc_signal<bool> e_write_n; \/\/left output data control pin.$/;" m class:tileempty core.h /^ sc_in<sc_uint<3> > empty; \/\/State of FIFO is full.$/;" m class:coreempty fifo.h /^ sc_out<sc_uint<3> > empty; \/\/State of FIFO is full.$/;" m class:virtual_fifoempty top.h /^ sc_signal<sc_uint<3> > empty; \/\/State of FIFO is full.$/;" m class:topfc router.h /^ sc_uint<FIFO_DEEP> fc;$/;" m class:routerfifo fifo.h /^ sc_fifo<bool> fifo, fifo1, fifo2;$/;" m class:virtual_fifofifo1 fifo.h /^ sc_fifo<bool> fifo, fifo1, fifo2;$/;" m class:virtual_fifofifo2 fifo.h /^ sc_fifo<bool> fifo, fifo1, fifo2;$/;" m class:virtual_fifofifo_to_core_sel core.h /^ sc_out<sc_uint<2> > fifo_to_core_sel; \/\/fifo select signal when receive data.$/;" m class:corefifo_to_router router.cc /^bool router :: fifo_to_router(sc_uint<3> sel, sc_uint<8> *address, sc_uint<8> addr, $/;" f class:routerfifo_to_x_sel fifo.h /^ sc_in<sc_uint<2> > fifo_to_x_sel; \/\/Fifo select signal when transfer data.$/;" m class:virtual_fifofn router.h /^ unsigned fn : 2; \/\/Fifo number.$/;" m struct:CACHEfull core.h /^ sc_in<sc_uint<3> > full; \/\/State of FIFO is empty.$/;" m class:corefull fifo.h /^ sc_out<sc_uint<3> > full; \/\/State of FIFO is empty.$/;" m class:virtual_fifofull top.h /^ sc_signal<sc_uint<3> > full; \/\/State of FIFO is empty.$/;" m class:tophead packet_header.h /^ HEAD_FLIT head;$/;" m struct:packetheader_decoder router.cc /^void router :: header_decoder(sc_uint<8> addr){$/;" f class:routerip_core tile.h /^ core *ip_core;$/;" m class:tileip_core top.h /^ core ip_core;$/;" m class:topmemory core.h /^ sc_uint<FIFO_DEEP> memory[100];$/;" m class:coren_data_in router.h /^ sc_in<bool> n_data_in; \/\/north nput data port.$/;" m class:routern_data_in tile.h /^ sc_signal<bool> n_data_in;$/;" m class:tilen_data_out router.h /^ sc_out<bool> n_data_out; \/\/north output data port.$/;" m class:routern_data_out tile.h /^ sc_signal<bool> n_data_out;$/;" m class:tilen_empty router.h /^ sc_in<sc_uint<3> > n_empty; \/\/State of FIFO is full.$/;" m class:routern_empty tile.h /^ sc_signal<sc_uint<3> > n_empty; \/\/State of FIFO is full.$/;" m class:tilen_fifo_to_router_sel router.h /^ sc_out<sc_uint<2> > n_fifo_to_router_sel; \/\/north select signal.$/;" m class:routern_fifo_to_router_sel tile.h /^ sc_signal<sc_uint<2> > n_fifo_to_router_sel; \/\/west select signal.$/;" m class:tilen_full router.h /^ sc_in<sc_uint<3> > n_full; \/\/State of FIFO is empty.$/;" m class:routern_full tile.h /^ sc_signal<sc_uint<3> > n_full; \/\/State of FIFO is empty.$/;" m class:tilen_raddress router.h /^ sc_uint<8> n_raddress;$/;" m class:routern_read_en router.h /^ sc_event n_read_en;$/;" m class:routern_read_n router.h /^ sc_out<bool> n_read_n; \/\/north input data control pin.$/;" m class:routern_read_n tile.h /^ sc_signal<bool> n_read_n; \/\/left input data control pin.$/;" m class:tilen_receive_data router.cc /^void router :: n_receive_data(){$/;" f class:routern_router_to_fifo_sel router.h /^ sc_out<sc_uint<2> > n_router_to_fifo_sel; \/\/north select signal.$/;" m class:routern_router_to_fifo_sel tile.h /^ sc_signal<sc_uint<2> > n_router_to_fifo_sel; \/\/west select signal.$/;" m class:tilen_transfer_data router.cc /^void router :: n_transfer_data(){$/;" f class:routern_waddress router.h /^ sc_uint<8> n_waddress;$/;" m class:routern_write_en router.h /^ sc_event n_write_en;$/;" m class:routern_write_n router.h /^ sc_out<bool> n_write_n; \/\/north output data control pin.$/;" m class:routern_write_n tile.h /^ sc_signal<bool> n_write_n; \/\/left output data control pin.$/;" m class:tilepacket packet_header.h /^typedef struct packet{$/;" spkt_size packet_header.h /^ unsigned pkt_size : 3; \/\/The number of flits. 2^4 = 16 Bytes.$/;" m struct:HEAD_FLITraddress core.h /^ sc_uint<8> raddress;$/;" m class:coreread_data core.cc /^bool core :: read_data(sc_uint<3> sel, sc_uint<8> addr)$/;" f class:coreread_en core.h /^ sc_event read_en;$/;" m class:coreread_n core.h /^ sc_out<bool> read_n; \/\/core input data control pin.$/;" m class:coreread_n fifo.h /^ sc_in<bool> read_n; \/\/Input data control pin.$/;" m class:virtual_fiforead_n top.h /^ sc_signal<bool> read_n; \/\/Input data control pin.$/;" m class:toprec_fifo top.h /^ virtual_fifo rec_fifo;$/;" m class:toprec_sel top.h /^ sc_signal<sc_uint<2> > rec_sel; \/\/Select fifo.$/;" m class:topreceive_data core.cc /^void core :: receive_data()$/;" f class:corereceive_data router.cc /^void router :: receive_data(sc_in<bool> *data_in, sc_out<bool> *read_n, sc_event *read_en, $/;" f class:routerreceive_fifo fifo.cc /^void virtual_fifo::receive_fifo()$/;" f class:virtual_fiforeceiver router.h /^ sc_event receiver;$/;" m class:routerreceiver_handle router.cc /^void router :: receiver_handle(){$/;" f class:routerreset_n router.h /^ sc_in<bool> reset_n;$/;" m class:routerrouter router.h /^ router(sc_module_name nm, int id, int column_num, int row_num): sc_module(nm){$/;" f class:routerrouter router.h /^class router : public sc_module{$/;" crouter_empty tile.h /^ sc_signal<sc_uint<3> > router_empty; \/\/State of FIFO is full.$/;" m class:tilerouter_fabric tile.h /^ router *router_fabric;$/;" m class:tilerouter_full tile.h /^ sc_signal<sc_uint<3> > router_full; \/\/State of FIFO is empty.$/;" m class:tilerouter_handle router.cc /^void router :: router_handle()$/;" f class:routerrouter_id router.h /^ sc_uint<6> router_id;$/;" m class:routerrouter_to_core_fifo tile.h /^ virtual_fifo *router_to_core_fifo;$/;" m class:tilerouter_to_fifo router.cc /^bool router :: router_to_fifo(sc_uint<3> sel, sc_uint<8> *address, sc_uint<8> addr, $/;" f class:routerrouter_to_fifo_read_n tile.h /^ sc_signal<bool> router_to_fifo_read_n; \/\/Input data control pin.$/;" m class:tilerouter_to_fifo_write_n tile.h /^ sc_signal<bool> router_to_fifo_write_n; \/\/Output data control pin a.$/;" m class:tilerow_num define.h /^ unsigned int row_num;$/;" m struct:NOC_INFOrst core.h /^ sc_in<bool> rst; \/\/reset signal.$/;" m class:corerst tile.h /^ sc_signal<bool> rst;$/;" m class:tilerst top.h /^ sc_signal<bool> rst;$/;" m class:tops_data_in router.h /^ sc_in<bool> s_data_in; \/\/south input data port.$/;" m class:routers_data_in tile.h /^ sc_signal<bool> s_data_in;$/;" m class:tiles_data_out router.h /^ sc_out<bool> s_data_out; \/\/south output data port.$/;" m class:routers_data_out tile.h /^ sc_signal<bool> s_data_out;$/;" m class:tiles_empty router.h /^ sc_in<sc_uint<3> > s_empty; \/\/State of FIFO is full.$/;" m class:routers_empty tile.h /^ sc_signal<sc_uint<3> > s_empty; \/\/State of FIFO is full.$/;" m class:tiles_fifo_to_router_sel router.h /^ sc_out<sc_uint<2> > s_fifo_to_router_sel; \/\/north select signal.$/;" m class:routers_fifo_to_router_sel tile.h /^ sc_signal<sc_uint<2> > s_fifo_to_router_sel; \/\/west select signal.$/;" m class:tiles_full router.h /^ sc_in<sc_uint<3> > s_full; \/\/State of FIFO is empty.$/;" m class:routers_full tile.h /^ sc_signal<sc_uint<3> > s_full; \/\/State of FIFO is empty.$/;" m class:tiles_raddress router.h /^ sc_uint<8> s_raddress;$/;" m class:routers_read_en router.h /^ sc_event s_read_en;$/;" m class:routers_read_n router.h /^ sc_out<bool> s_read_n; \/\/south input data control pin.$/;" m class:routers_read_n tile.h /^ sc_signal<bool> s_read_n; \/\/left input data control pin.$/;" m class:tiles_receive_data router.cc /^void router :: s_receive_data(){$/;" f class:routers_router_to_fifo_sel router.h /^ sc_out<sc_uint<2> > s_router_to_fifo_sel; \/\/north select signal.$/;" m class:routers_router_to_fifo_sel tile.h /^ sc_signal<sc_uint<2> > s_router_to_fifo_sel; \/\/west select signal.$/;" m class:tiles_transfer_data router.cc /^void router :: s_transfer_data(){$/;" f class:routers_waddress router.h /^ sc_uint<8> s_waddress;$/;" m class:routers_write_en router.h /^ sc_event s_write_en;$/;" m class:routers_write_n router.h /^ sc_out<bool> s_write_n; \/\/south output data control pin.$/;" m class:routers_write_n tile.h /^ sc_signal<bool> s_write_n; \/\/left output data control pin.$/;" m class:tilesc_debug core.h /^ sc_event sc_debug;$/;" m class:coresc_main noc.cc /^int sc_main(int argc, char *argv[])$/;" fsel_fifo core.h /^ sc_uint<3> sel_fifo;$/;" m class:coresequence packet_header.h /^ unsigned sequence : 4; \/\/The sequence of flits.$/;" m struct:HEAD_FLITswitch_table router.h /^ sc_uint<15> switch_table[15]; \/\/switching table.$/;" m class:routertile tile.h /^class tile: public sc_module{$/;" ctile_id define.h /^ unsigned char tile_id;$/;" m struct:NOC_INFOtop top.h /^ top(sc_module_name nm):sc_module(nm), ip_core("ip_core"), rec_fifo("rec_fifo"){$/;" f class:toptop top.h /^class top: public sc_module{$/;" ctr_sel top.h /^ sc_signal<sc_uint<2> > tr_sel;$/;" m class:toptransfer_data core.cc /^void core :: transfer_data()$/;" f class:coretransfer_data router.cc /^void router :: transfer_data(sc_out<bool> *data_out, sc_out<bool> *write_n, sc_event *write_en,$/;" f class:routertransfer_fifo fifo.cc /^void virtual_fifo::transfer_fifo()$/;" f class:virtual_fifotransmitter router.h /^ sc_event transmitter;$/;" m class:routertransmitter_handle router.cc /^void router :: transmitter_handle(){$/;" f class:routertype packet_header.h /^ unsigned type : 1;$/;" m struct:body_filttype packet_header.h /^ unsigned type : 2; \/\/'0' is header flit, '1' is body flit, and '2' is tail flit.$/;" m struct:HEAD_FLITvirtual_fifo fifo.h /^class virtual_fifo : public sc_module{$/;" cw_data_in router.h /^ sc_in<bool> w_data_in; \/\/west input data port.$/;" m class:routerw_data_in tile.h /^ sc_signal<bool> w_data_in;$/;" m class:tilew_data_out router.h /^ sc_out<bool> w_data_out; \/\/west output data port.$/;" m class:routerw_data_out tile.h /^ sc_signal<bool> w_data_out;$/;" m class:tilew_empty router.h /^ sc_in<sc_uint<3> > w_empty; \/\/State of FIFO is full.$/;" m class:routerw_empty tile.h /^ sc_signal<sc_uint<3> > w_empty; \/\/State of FIFO is full.$/;" m class:tilew_fifo_to_router_sel router.h /^ sc_out<sc_uint<2> > w_fifo_to_router_sel; \/\/west select signal.$/;" m class:routerw_fifo_to_router_sel tile.h /^ sc_signal<sc_uint<2> > w_fifo_to_router_sel; \/\/west select signal.$/;" m class:tilew_full router.h /^ sc_in<sc_uint<3> > w_full; \/\/State of FIFO is empty.$/;" m class:routerw_full tile.h /^ sc_signal<sc_uint<3> > w_full; \/\/State of FIFO is empty.$/;" m class:tilew_raddress router.h /^ sc_uint<8> w_raddress;$/;" m class:routerw_read_en router.h /^ sc_event w_read_en;$/;" m class:routerw_read_n router.h /^ sc_out<bool> w_read_n; \/\/left input data control pin.$/;" m class:routerw_read_n tile.h /^ sc_signal<bool> w_read_n; \/\/left input data control pin.$/;" m class:tilew_receive_data router.cc /^void router :: w_receive_data(){$/;" f class:routerw_router_to_fifo_sel router.h /^ sc_out<sc_uint<2> > w_router_to_fifo_sel; \/\/west select signal.$/;" m class:routerw_router_to_fifo_sel tile.h /^ sc_signal<sc_uint<2> > w_router_to_fifo_sel; \/\/west select signal.$/;" m class:tilew_transfer_data router.cc /^void router :: w_transfer_data(){$/;" f class:routerw_waddress router.h /^ sc_uint<8> w_waddress;$/;" m class:routerw_write_en router.h /^ sc_event w_write_en;$/;" m class:routerw_write_n router.h /^ sc_out<bool> w_write_n; \/\/left output data control pin.$/;" m class:routerw_write_n tile.h /^ sc_signal<bool> w_write_n; \/\/left output data control pin.$/;" m class:tilewaddress core.h /^ sc_uint<8> waddress;$/;" m class:corewcore_to_fifo_sel tile.h /^ sc_signal<sc_uint<2> > wcore_to_fifo_sel; \/\/to read data to fifo between core and fifo.$/;" m class:tilewfifo_to_core_sel tile.h /^ sc_signal<sc_uint<2> > wfifo_to_core_sel; \/\/to write data to fifo between core and fifo.$/;" m class:tilewfifo_to_router_sel tile.h /^ sc_signal<sc_uint<2> > wfifo_to_router_sel; \/\/to read data to fifo between fifo and router.$/;" m class:tilewr router.h /^ unsigned wr : 1; \/\/Write\/Read.$/;" m struct:CACHEwrite_data core.cc /^bool core :: write_data(sc_uint<3> sel, sc_uint<8> addr)$/;" f class:corewrite_en core.h /^ sc_event write_en;$/;" m class:corewrite_n core.h /^ sc_out<bool> write_n; \/\/core output data control pin.$/;" m class:corewrite_n fifo.h /^ sc_in<bool> write_n; \/\/Output data control pin a.$/;" m class:virtual_fifowrite_n top.h /^ sc_signal<bool> write_n; \/\/Output data control pin a.$/;" m class:topwrouter_to_fifo_sel tile.h /^ sc_signal<sc_uint<2> > wrouter_to_fifo_sel; \/\/to write data to fifo between fifo and router.$/;" m class:tilex_num router.h /^ sc_uint<6> x_num;$/;" m class:routerx_to_fifo_sel fifo.h /^ sc_in<sc_uint<2> > x_to_fifo_sel; \/\/Fifo select signal when receive data.$/;" m class:virtual_fifoy_num router.h /^ sc_uint<6> y_num;$/;" m class:router