Subversion Repositories numbert_sort_device

 
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================
 
module DE2_115_VGA(
 
	//////////// CLOCK //////////
	CLOCK_50,
	CLOCK2_50,
	CLOCK3_50,
 
	//////////// KEY //////////
	KEY,
 
	//////////// SW //////////
	SW,
 
	//////////// SEG7 //////////
	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,
 
	//////////// VGA //////////
	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS 
);
 
//=======================================================
//  PARAMETER declarations
//=======================================================
 
parameter R_SZ= 512;
 
 
//=======================================================
//  PORT declarations
//=======================================================
 
//////////// CLOCK //////////
input 		          		CLOCK_50;
input 		          		CLOCK2_50;
input 		          		CLOCK3_50;
 
//////////// KEY //////////
input 		     [3:0]		KEY;
 
//////////// SW //////////
input 		    [17:0]		SW;
 
//////////// SEG7 //////////
output		     [6:0]		HEX0;
output		     [6:0]		HEX1;
output		     [6:0]		HEX2;
output		     [6:0]		HEX3;
output		     [6:0]		HEX4;
output		     [6:0]		HEX5;
output		     [6:0]		HEX6;
output		     [6:0]		HEX7;
 
//////////// VGA //////////
output		     [7:0]		VGA_B;
output		          		VGA_BLANK_N;
output		          		VGA_CLK;
output		     [7:0]		VGA_G;
output		          		VGA_HS;
output		     [7:0]		VGA_R;
output		          		VGA_SYNC_N;
output		          		VGA_VS;
 
 
//=======================================================
//  REG/WIRE declarations
//=======================================================
 
wire			VGA_CTRL_CLK_1240x1024;
wire			VGA_CTRL_CLK= VGA_CTRL_CLK_1240x1024;
assign VGA_CLK= VGA_CTRL_CLK;
 
wire			VGA_HS_1240x1024;			
wire			VGA_VS_1240x1024;	
assign			VGA_HS= VGA_HS_1240x1024;	//	VGA H_SYNC
assign			VGA_VS= VGA_VS_1240x1024;	//	VGA V_SYNC
 
wire	[11:0]	mVGA_X;
wire	[11:0]	mVGA_Y;
 
wire	[9:0]	mVGA_R;
wire	[9:0]	mVGA_G;
wire	[9:0]	mVGA_B;
 
wire	[9:0]	sVGA_R_1240x1024;
wire	[9:0]	sVGA_G_1240x1024;
wire	[9:0]	sVGA_B_1240x1024;
wire	[9:0]	sVGA_R= sVGA_R_1240x1024;
wire	[9:0]	sVGA_G= sVGA_G_1240x1024;
wire	[9:0]	sVGA_B= sVGA_B_1240x1024;
 
 
assign	VGA_R	=	sVGA_R[7:0];
assign	VGA_G	=	sVGA_G[7:0];
assign	VGA_B	=	sVGA_B[7:0];
 
//=======================================================
//  Structural coding
//=======================================================
 
VGA_CLK		u1_1240x1024
		(	.inclk0(CLOCK_50),
			.c0( VGA_CTRL_CLK_1240x1024 )
		);
		defparam u1_1240x1024.PLL_MUL= 54;
		defparam u1_1240x1024.PLL_DIV= 25;
 
 
VGA_Ctrl	u2_1240x1024
		(	//	Host Side
			.oCurrent_X( mVGA_X),
			.oCurrent_Y( mVGA_Y),
			.iRed( mVGA_R),
			.iGreen( mVGA_G),
			.iBlue( mVGA_B),
			//	VGA Side
			.oVGA_R( sVGA_R_1240x1024 ),
			.oVGA_G( sVGA_G_1240x1024 ),
			.oVGA_B( sVGA_B_1240x1024 ),
			.oVGA_HS( VGA_HS_1240x1024 ),
			.oVGA_VS( VGA_VS_1240x1024 ),
			.oVGA_SYNC( VGA_SYNC_N ),
			.oVGA_BLANK( VGA_BLANK_N ),
			.oVGA_CLOCK(),
			//	Control Signal
			.iCLK( VGA_CTRL_CLK),
			.iRST_N( KEY[0]),
			.les_btn( KEY[2])
		);
		defparam	u2_1240x1024.H_FRONT	=	48;
		defparam	u2_1240x1024.H_SYNC	=	112;
		defparam	u2_1240x1024.H_BACK	=	248;
		defparam	u2_1240x1024.H_ACT	=	1280;
		defparam	u2_1240x1024.V_FRONT	=	1;
		defparam	u2_1240x1024.V_SYNC	=	3;
		defparam	u2_1240x1024.V_BACK	=	38;
		defparam	u2_1240x1024.V_ACT	=	1024;
 
wire [31:0]VGenOut;
parameter RES_X_H= 1240;
parameter RES_Y_H= 1024;
parameter XY_STEP_H= 7;
wire signed [11:0] x;
wire signed [11:0] y;
assign x= (mVGA_X- RES_X_H/2);
assign y= (mVGA_Y- RES_Y_H/2);
wire [31:0] X_in= x<<<XY_STEP_H;
wire [31:0] Y_in= y<<<XY_STEP_H;
 
VGA_Pattern #( R_SZ )	u3
		(	//	Read Out Side
			.oRed(mVGA_R),
			.oGreen(mVGA_G),
			.oBlue(mVGA_B),
			.iVGA_X(mVGA_X),
			.iVGA_Y(mVGA_Y),
			.iVGA_CLK(VGA_CTRL_CLK),
			//	Control Signals
			.iRST_n(KEY[0]),
			.iColor_SW(SW),
			.endFrame(VGA_VS),
			.dbg_val(dbg_val)
		);
 
wire [63:0] dbg_val;
wire [15:0] indicated_part;		
wire seg_first;
 
dbg_7seg dbg_num 
		(  .val( dbg_val ), 
			.show_next(KEY[2]), 
			.part( indicated_part ), 
			.is_first( seg_first ) );		
 
SEG7_LUT_4	u0
		(	.oSEG0(HEX0),
			.oSEG1(HEX1),
			.oSEG2(HEX2),
			.oSEG3(HEX3),
			.iDIG( indicated_part )
		);
 
 
endmodule