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[/] [oc54x/] [trunk/] [rtl/] [verilog/] [oc54_exp.v] - Rev 5
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///////////////////////////////////////////////////////////////////// //// //// //// OpenCores54 DSP, Exponent Encoder //// //// //// //// Author: Richard Herveille //// //// richard@asics.ws //// //// www.asics.ws //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2002 Richard Herveille //// //// richard@asics.ws //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// // // Xilinx Virtex-E WC: 116 CLB slices @ 74MHz, pass 4 // // CVS Log // // $Id: oc54_exp.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $ // // $Date: 2002-04-10 09:34:41 $ // $Revision: 1.1.1.1 $ // $Author: rherveille $ // $Locker: $ // $State: Exp $ // // Change History: // $Log: not supported by cvs2svn $ `include "timescale.v" module oc54_exp ( clk, ena, sel_acc, a, b, bp_ar, bp_br, bp_a, bp_b, result ); // // parameters // // // inputs & outputs // input clk; input ena; input sel_acc; // select accumulator input [39:0] a, b; // accumulator inputs input [39:0] bp_ar, bp_br; // bypass accumulator a / b input bp_a, bp_b; // bypass selects output [ 5:0] result; reg [5:0] result; // // variables // reg [39:0] acc; ///////////////// // module body // ///////////////// 34('1') - 1(sign bit) - 8 // // generate input selection // // input selection always@(posedge clk) if (ena) if (sel_acc) acc = bp_b ? bp_br : b; else acc = bp_a ? bp_ar : a; // // Generate exponent encoder // // The result of the exponent encoder is the number of leading // redundant bits, except the sign-bit, -8. Exp is in the -8 to +31 range. // 00_0110 -> 11_1001 -> 11_1010 always@(posedge clk) if (ena) casex (acc) // synopsis full_case parallel_case // // positive numbers // 40'b01??_????_????_????_????_????_????_????_????_????: result <= #1 6'h38; // 1 (leading red. bit) - 1 (sign bit) - 8 = -8 40'b001?_????_????_????_????_????_????_????_????_????: result <= #1 6'h39; // 2 (leading red. bit) - 1 (sign bit) - 8 = -7 40'b0001_????_????_????_????_????_????_????_????_????: result <= #1 6'h3a; // 3 (leading red. bit) - 1 (sign bit) - 8 = -6 40'b0000_1???_????_????_????_????_????_????_????_????: result <= #1 6'h3b; // 4 (leading red. bit) - 1 (sign bit) - 8 = -5 40'b0000_01??_????_????_????_????_????_????_????_????: result <= #1 6'h3c; // 5 (leading red. bit) - 1 (sign bit) - 8 = -4 40'b0000_001?_????_????_????_????_????_????_????_????: result <= #1 6'h3d; // 6 (leading red. bit) - 1 (sign bit) - 8 = -3 40'b0000_0001_????_????_????_????_????_????_????_????: result <= #1 6'h3e; // 7 (leading red. bit) - 1 (sign bit) - 8 = -2 40'b0000_0000_1???_????_????_????_????_????_????_????: result <= #1 6'h3f; // 8 (leading red. bit) - 1 (sign bit) - 8 = -1 40'b0000_0000_01??_????_????_????_????_????_????_????: result <= #1 6'h00; // 9 (leading red. bit) - 1 (sign bit) - 8 = 0 40'b0000_0000_001?_????_????_????_????_????_????_????: result <= #1 6'h01; //10 (leading red. bit) - 1 (sign bit) - 8 = 1 40'b0000_0000_0001_????_????_????_????_????_????_????: result <= #1 6'h02; //11 (leading red. bit) - 1 (sign bit) - 8 = 2 40'b0000_0000_0000_1???_????_????_????_????_????_????: result <= #1 6'h03; //12 (leading red. bit) - 1 (sign bit) - 8 = 3 40'b0000_0000_0000_01??_????_????_????_????_????_????: result <= #1 6'h04; //13 (leading red. bit) - 1 (sign bit) - 8 = 4 40'b0000_0000_0000_001?_????_????_????_????_????_????: result <= #1 6'h05; //14 (leading red. bit) - 1 (sign bit) - 8 = 5 40'b0000_0000_0000_0001_????_????_????_????_????_????: result <= #1 6'h06; //15 (leading red. bit) - 1 (sign bit) - 8 = 6 40'b0000_0000_0000_0000_1???_????_????_????_????_????: result <= #1 6'h07; //16 (leading red. bit) - 1 (sign bit) - 8 = 7 40'b0000_0000_0000_0000_01??_????_????_????_????_????: result <= #1 6'h08; //17 (leading red. bit) - 1 (sign bit) - 8 = 8 40'b0000_0000_0000_0000_001?_????_????_????_????_????: result <= #1 6'h09; //18 (leading red. bit) - 1 (sign bit) - 8 = 9 40'b0000_0000_0000_0000_0001_????_????_????_????_????: result <= #1 6'h0a; //19 (leading red. bit) - 1 (sign bit) - 8 =10 40'b0000_0000_0000_0000_0000_1???_????_????_????_????: result <= #1 6'h0b; //20 (leading red. bit) - 1 (sign bit) - 8 =11 40'b0000_0000_0000_0000_0000_01??_????_????_????_????: result <= #1 6'h0c; //21 (leading red. bit) - 1 (sign bit) - 8 =12 40'b0000_0000_0000_0000_0000_001?_????_????_????_????: result <= #1 6'h0d; //22 (leading red. bit) - 1 (sign bit) - 8 =13 40'b0000_0000_0000_0000_0000_0001_????_????_????_????: result <= #1 6'h0e; //23 (leading red. bit) - 1 (sign bit) - 8 =14 40'b0000_0000_0000_0000_0000_0000_1???_????_????_????: result <= #1 6'h0f; //24 (leading red. bit) - 1 (sign bit) - 8 =15 40'b0000_0000_0000_0000_0000_0000_01??_????_????_????: result <= #1 6'h10; //25 (leading red. bit) - 1 (sign bit) - 8 =16 40'b0000_0000_0000_0000_0000_0000_001?_????_????_????: result <= #1 6'h11; //26 (leading red. bit) - 1 (sign bit) - 8 =17 40'b0000_0000_0000_0000_0000_0000_0001_????_????_????: result <= #1 6'h12; //27 (leading red. bit) - 1 (sign bit) - 8 =18 40'b0000_0000_0000_0000_0000_0000_0000_1???_????_????: result <= #1 6'h13; //28 (leading red. bit) - 1 (sign bit) - 8 =19 40'b0000_0000_0000_0000_0000_0000_0000_01??_????_????: result <= #1 6'h14; //29 (leading red. bit) - 1 (sign bit) - 8 =20 40'b0000_0000_0000_0000_0000_0000_0000_001?_????_????: result <= #1 6'h15; //30 (leading red. bit) - 1 (sign bit) - 8 =21 40'b0000_0000_0000_0000_0000_0000_0000_0001_????_????: result <= #1 6'h16; //31 (leading red. bit) - 1 (sign bit) - 8 =22 40'b0000_0000_0000_0000_0000_0000_0000_0000_1???_????: result <= #1 6'h17; //32 (leading red. bit) - 1 (sign bit) - 8 =23 40'b0000_0000_0000_0000_0000_0000_0000_0000_01??_????: result <= #1 6'h18; //33 (leading red. bit) - 1 (sign bit) - 8 =24 40'b0000_0000_0000_0000_0000_0000_0000_0000_001?_????: result <= #1 6'h19; //34 (leading red. bit) - 1 (sign bit) - 8 =25 40'b0000_0000_0000_0000_0000_0000_0000_0000_0001_????: result <= #1 6'h1a; //35 (leading red. bit) - 1 (sign bit) - 8 =26 40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_1???: result <= #1 6'h1b; //36 (leading red. bit) - 1 (sign bit) - 8 =27 40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_01??: result <= #1 6'h1c; //37 (leading red. bit) - 1 (sign bit) - 8 =28 40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_001?: result <= #1 6'h1d; //38 (leading red. bit) - 1 (sign bit) - 8 =29 40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0001: result <= #1 6'h1e; //39 (leading red. bit) - 1 (sign bit) - 8 =30 40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000: result <= #1 6'h1f; //40 (leading red. bit) - 1 (sign bit) - 8 =31 // // negative numbers // 40'b10??_????_????_????_????_????_????_????_????_????: result <= #1 6'h38; // 1 (leading red. bit) - 1 (sign bit) - 8 = -8 40'b110?_????_????_????_????_????_????_????_????_????: result <= #1 6'h39; // 2 (leading red. bit) - 1 (sign bit) - 8 = -7 40'b1110_????_????_????_????_????_????_????_????_????: result <= #1 6'h3a; // 3 (leading red. bit) - 1 (sign bit) - 8 = -6 40'b1111_0???_????_????_????_????_????_????_????_????: result <= #1 6'h3b; // 4 (leading red. bit) - 1 (sign bit) - 8 = -5 40'b1111_10??_????_????_????_????_????_????_????_????: result <= #1 6'h3c; // 5 (leading red. bit) - 1 (sign bit) - 8 = -4 40'b1111_110?_????_????_????_????_????_????_????_????: result <= #1 6'h3d; // 6 (leading red. bit) - 1 (sign bit) - 8 = -3 40'b1111_1110_????_????_????_????_????_????_????_????: result <= #1 6'h3e; // 7 (leading red. bit) - 1 (sign bit) - 8 = -2 40'b1111_1111_0???_????_????_????_????_????_????_????: result <= #1 6'h3f; // 8 (leading red. bit) - 1 (sign bit) - 8 = -1 40'b1111_1111_10??_????_????_????_????_????_????_????: result <= #1 6'h00; // 9 (leading red. bit) - 1 (sign bit) - 8 = 0 40'b1111_1111_110?_????_????_????_????_????_????_????: result <= #1 6'h01; //10 (leading red. bit) - 1 (sign bit) - 8 = 1 40'b1111_1111_1110_????_????_????_????_????_????_????: result <= #1 6'h02; //11 (leading red. bit) - 1 (sign bit) - 8 = 2 40'b1111_1111_1111_0???_????_????_????_????_????_????: result <= #1 6'h03; //12 (leading red. bit) - 1 (sign bit) - 8 = 3 40'b1111_1111_1111_10??_????_????_????_????_????_????: result <= #1 6'h04; //13 (leading red. bit) - 1 (sign bit) - 8 = 4 40'b1111_1111_1111_110?_????_????_????_????_????_????: result <= #1 6'h05; //14 (leading red. bit) - 1 (sign bit) - 8 = 5 40'b1111_1111_1111_1110_????_????_????_????_????_????: result <= #1 6'h06; //15 (leading red. bit) - 1 (sign bit) - 8 = 6 40'b1111_1111_1111_1111_0???_????_????_????_????_????: result <= #1 6'h07; //16 (leading red. bit) - 1 (sign bit) - 8 = 7 40'b1111_1111_1111_1111_10??_????_????_????_????_????: result <= #1 6'h08; //17 (leading red. bit) - 1 (sign bit) - 8 = 8 40'b1111_1111_1111_1111_110?_????_????_????_????_????: result <= #1 6'h09; //18 (leading red. bit) - 1 (sign bit) - 8 = 9 40'b1111_1111_1111_1111_1110_????_????_????_????_????: result <= #1 6'h0a; //19 (leading red. bit) - 1 (sign bit) - 8 =10 40'b1111_1111_1111_1111_1111_0???_????_????_????_????: result <= #1 6'h0b; //20 (leading red. bit) - 1 (sign bit) - 8 =11 40'b1111_1111_1111_1111_1111_10??_????_????_????_????: result <= #1 6'h0c; //21 (leading red. bit) - 1 (sign bit) - 8 =12 40'b1111_1111_1111_1111_1111_110?_????_????_????_????: result <= #1 6'h0d; //22 (leading red. bit) - 1 (sign bit) - 8 =13 40'b1111_1111_1111_1111_1111_1110_????_????_????_????: result <= #1 6'h0e; //23 (leading red. bit) - 1 (sign bit) - 8 =14 40'b1111_1111_1111_1111_1111_1111_0???_????_????_????: result <= #1 6'h0f; //24 (leading red. bit) - 1 (sign bit) - 8 =15 40'b1111_1111_1111_1111_1111_1111_10??_????_????_????: result <= #1 6'h10; //25 (leading red. bit) - 1 (sign bit) - 8 =16 40'b1111_1111_1111_1111_1111_1111_110?_????_????_????: result <= #1 6'h11; //26 (leading red. bit) - 1 (sign bit) - 8 =17 40'b1111_1111_1111_1111_1111_1111_1110_????_????_????: result <= #1 6'h12; //27 (leading red. bit) - 1 (sign bit) - 8 =18 40'b1111_1111_1111_1111_1111_1111_1111_0???_????_????: result <= #1 6'h13; //28 (leading red. bit) - 1 (sign bit) - 8 =19 40'b1111_1111_1111_1111_1111_1111_1111_10??_????_????: result <= #1 6'h14; //29 (leading red. bit) - 1 (sign bit) - 8 =20 40'b1111_1111_1111_1111_1111_1111_1111_110?_????_????: result <= #1 6'h15; //30 (leading red. bit) - 1 (sign bit) - 8 =21 40'b1111_1111_1111_1111_1111_1111_1111_1110_????_????: result <= #1 6'h16; //31 (leading red. bit) - 1 (sign bit) - 8 =22 40'b1111_1111_1111_1111_1111_1111_1111_1111_0???_????: result <= #1 6'h17; //32 (leading red. bit) - 1 (sign bit) - 8 =23 40'b1111_1111_1111_1111_1111_1111_1111_1111_10??_????: result <= #1 6'h18; //33 (leading red. bit) - 1 (sign bit) - 8 =24 40'b1111_1111_1111_1111_1111_1111_1111_1111_110?_????: result <= #1 6'h19; //34 (leading red. bit) - 1 (sign bit) - 8 =25 40'b1111_1111_1111_1111_1111_1111_1111_1111_1110_????: result <= #1 6'h1a; //35 (leading red. bit) - 1 (sign bit) - 8 =26 40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_0???: result <= #1 6'h1b; //36 (leading red. bit) - 1 (sign bit) - 8 =27 40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_10??: result <= #1 6'h1c; //37 (leading red. bit) - 1 (sign bit) - 8 =28 40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_110?: result <= #1 6'h1d; //38 (leading red. bit) - 1 (sign bit) - 8 =29 40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_1110: result <= #1 6'h1e; //39 (leading red. bit) - 1 (sign bit) - 8 =30 40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111: result <= #1 6'h1f; //40 (leading red. bit) - 1 (sign bit) - 8 =31 endcase endmodule