Subversion Repositories oc_axi_bfm

// avalon_dma_tb.v
 
// Generated using ACDS version 19.1 670
 
`timescale 1 ps / 1 ps
module avalon_dma_tb (
	);
 
  integer i;
  reg [31:0] i_r;
 
 
  reg   [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r;
  reg   [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2_r;
  reg  [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3_r;
  reg  [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_r;  
 
	wire         avalon_dma_inst_clk_bfm_clk_clk;                                   // avalon_dma_inst_clk_bfm:clk -> [avalon_dma_inst:clk_clk, avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:clk, avalon_dma_inst_reset_bfm:clk]
	wire         avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4;             // avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_4 -> avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_4
	wire   [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_5 -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_5
	wire  [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_1;             // avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_1 -> avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_1
	wire   [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_2 -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_2
	wire  [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_3 -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_3
	wire  [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal;   // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal
	wire         avalon_dma_inst_reset_bfm_reset_reset;                             // avalon_dma_inst_reset_bfm:reset -> avalon_dma_inst:reset_reset_n
 
  assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5 = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r;
  assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2 = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2_r;
  assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3 = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3_r;
  assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal   = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_r;
 
	avalon_dma avalon_dma_inst (
		.clk_clk                               (avalon_dma_inst_clk_bfm_clk_clk),                                   //                      clk.clk
		.oc_axi_lite_bfm_0_driver_new_signal   (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal),   // oc_axi_lite_bfm_0_driver.new_signal
		.oc_axi_lite_bfm_0_driver_new_signal_1 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_1),             //                         .new_signal_1
		.oc_axi_lite_bfm_0_driver_new_signal_2 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2), //                         .new_signal_2
		.oc_axi_lite_bfm_0_driver_new_signal_3 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3), //                         .new_signal_3
		.oc_axi_lite_bfm_0_driver_new_signal_4 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4),             //                         .new_signal_4
		.oc_axi_lite_bfm_0_driver_new_signal_5 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5), //                         .new_signal_5
		.reset_reset_n                         (avalon_dma_inst_reset_bfm_reset_reset)                              //                    reset.reset_n
	);
 
	altera_avalon_clock_source #(
		.CLOCK_RATE (50000000),
		.CLOCK_UNIT (1)
	) avalon_dma_inst_clk_bfm (
		.clk (avalon_dma_inst_clk_bfm_clk_clk)  // clk.clk
	);
 
/*
	altera_conduit_bfm avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm (
		.clk              (avalon_dma_inst_clk_bfm_clk_clk),                                   //     clk.clk
		.sig_new_signal   (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal),   // conduit.new_signal
		.sig_new_signal_1 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_1),             //        .new_signal_1
		.sig_new_signal_2 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2), //        .new_signal_2
		.sig_new_signal_3 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3), //        .new_signal_3
		.sig_new_signal_4 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4),             //        .new_signal_4
		.sig_new_signal_5 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5), //        .new_signal_5
		.reset            (1'b0)                                                               // (terminated)
	);
*/
	altera_avalon_reset_source #(
		.ASSERT_HIGH_RESET    (0),
		.INITIAL_RESET_CYCLES (50)
	) avalon_dma_inst_reset_bfm (
		.reset (avalon_dma_inst_reset_bfm_reset_reset), // reset.reset_n
		.clk   (avalon_dma_inst_clk_bfm_clk_clk)        //   clk.clk
	);
 
/*
		.addr             (oc_axi_lite_bfm_0_driver_new_signal),   //  driver.new_signal
		.r_data           (oc_axi_lite_bfm_0_driver_new_signal_1), //        .new_signal_1
		.transaction_type (oc_axi_lite_bfm_0_driver_new_signal_2), //        .new_signal_2
		.w_data           (oc_axi_lite_bfm_0_driver_new_signal_3), //        .new_signal_3
		.done             (oc_axi_lite_bfm_0_driver_new_signal_4), //        .new_signal_4
		.start            (oc_axi_lite_bfm_0_driver_new_signal_5), //        .new_signal_5
*/
 
  initial begin
    #2000000
 
    i_r = 32'h00000000;
 
    for(i = 0; i < 4096; i=i+4)
    begin
      write(i_r, 32'hdeadbeef);
      i_r = i_r + 4;
    end
 
    write(32'h00002004, 32'h00000000); // read address
    write(32'h00002008, 32'h00001000); // write address
    write(32'h0000200C, 32'h00001000); // length
    write(32'h00002018, 32'h0000000a); // GO and WORD
 
 
  end
 
 
  task write;
    input [31:0] addr;
    input [31:0] data;
    begin
      $display("In task\n");
      avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_r = addr;       //addr
      avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3_r = data;     // data
      avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2_r  = 1'b0;    // write - transaction type
      avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r = 1'b1;     // start
 
      wait(avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4);      // done
      avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r = 1'b0;     // start
 
      wait(~avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4);     // done
    end
  endtask
 
endmodule