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[/] [oms8051mini/] [trunk/] [example/] [systemverilog/] [assertion/] [test4/] [sim.log] - Rev 13
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ncxlmode: 11.10-s021: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
TOOL: ncxlmode 11.10-s021: Started on Aug 01, 2014 at 13:38:57 IST
ncxlmode
+access+rcw
test.sv
-l
sim.log
file: test.sv
module worklib.goto_assertion:sv
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.goto_assertion:sv <0x50a1299e>
streams: 14, words: 8088
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 19 19
Always blocks: 9 9
Initial blocks: 7 7
Assertions: 2 2
Writing initial simulation snapshot: worklib.goto_assertion:sv
Loading snapshot worklib.goto_assertion:sv .................... Done
ncsim> source /tools/INCISIV111/tools/inca/files/ncsimrc
ncsim> run
req ##1 (busy [->3]) ##1 gnt;
|
ncsim: *E,ASRTST (./test.sv,37): (time 225 NS) Assertion goto_assertion.cool_way_assert has failed (8 cycles, starting 183 NS)
req ##1 ((!busy ##1 busy) [*3]) ##1 gnt;
|
ncsim: *E,ASRTST (./test.sv,36): (time 225 NS) Assertion goto_assertion.boring_way_assert has failed (8 cycles, starting 183 NS)
Simulation complete via $finish(1) at time 261 NS + 0
./test.sv:49 #30 $finish;
ncsim> exit
TOOL: ncxlmode 11.10-s021: Exiting on Aug 01, 2014 at 13:38:59 IST (total: 00:00:02)