OpenCores
URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [verif/] [glog/] [modelsim/] [int_sort.log] - Rev 30

Go to most recent revision | Compare with Previous | Blame | View Log

Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl 

# 10.1b

# vsim +INTERNAL_ROM -do run.do -c tb_top 
# //  ModelSim ACTEL 10.1b Apr 27 2012 
# //
# //  Copyright 1991-2012 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
# 
#         Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
# 
#         Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
# 
#         Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
# 
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
# 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
# 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
# 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
# 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
# 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
# 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
# 
# do run.do 
# i : 02
# i : 00
# i : 08
# i : 12
# i : 01
# i : 1f
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED 
################################

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.