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<td class=xl106 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
CPU Core Generics</td>
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<td class=xl67></td>
<td class=xl68></td>
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<tr height=20 style='height:15.0pt'>
<td height=20 class=xl69 style='height:15.0pt'>Option</td>
<td class=xl69>Argument Type</td>
<td class=xl70>Default</td>
<td class=xl72 width=893 style='width:670pt'>Description</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Program_Start_Addr</td>
<td class=xl76 style='border-top:none;border-left:none'>16-bit Address</td>
<td class=xl103 style='border-top:none;border-left:none'>x"0000"</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Initial
program counter location</td>
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<td height=20 class=xl73 style='height:15.0pt;border-top:none'>ISR_Start_Addr</td>
<td class=xl73 style='border-top:none;border-left:none'>16-bit Address</td>
<td class=xl74 style='border-top:none;border-left:none'>x"FFF0"</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
the initial location of the interrupt vector table</td>
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<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Stack_Start_Addr</td>
<td class=xl76 style='border-top:none;border-left:none'>16-bit Address</td>
<td class=xl103 style='border-top:none;border-left:none'>x"03FF"</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Initial
location of the CPU Stack - Must be located in accessible RAM</td>
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<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Allow_Stack_Address_Move</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
false, the RSP instruction will reset the stack pointer to
"Stack_Start_Addr" by default. If true, the RSP instruction will
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
depending on the status of the specified ALU flag bit.</td>
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<td height=80 class=xl76 style='height:60.0pt;border-top:none'>Stack_Xfer_Flag</td>
<td class=xl76 style='border-top:none;border-left:none'>Integer 0-7</td>
<td class=xl103 style='border-top:none;border-left:none'>PSR_GP4</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Specifies
which processor flag controls the behavior of RSP when
'Allow_Stack_Address_move' is true. If the specified bit is clear ('0'), the
RSP instruction will transfer the stack pointer to R1:R0 (SP -> R1:R0),
otherwise, if it is true ('1'), the RSP instruction will set the stack
pointer from R1:R0 ( R1:R0 -> SP ). Any of the 8 CPU flags may be
specified, but the intent was to use FL_GP[1-4], as these are purely under
software control and are not otherwise modified by the ALU.</td>
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<td height=80 class=xl73 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
true, indexed instructions such as LDX, LDO, STX, STO will automatically
increment if an odd register is specified. The effect is similar to a normal
indexed instruction followed by an UPP instruction on the same register pair.
For example, LDX R5 (or LDX R4++) will result in R0 getting the data stored
at the address specified by R5:R4. Afterwards, the register pair R5:R4 will
be incremented by 1. If false, specifying either register in a register pair
will result in normal behavior.</td>
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<td height=40 class=xl76 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
<td class=xl76 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl103 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>If
true, the BRK instruction will cause the processor to halt as if an INT
instruction was executed, but without triggering an interrupt. This is useful
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
simply causes the CPU to execute 5 NOP cycles.</td>
</tr>
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<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Enable_NMI</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>TRUE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
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<td height=40 class=xl76 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
<td class=xl76 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl103 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
interrupts from initiating an ISR if the I-bit is set, making ISRs
sequential. This potentially blocks interrupt priority by allowing a lower
level interrupt to block a higher level interrupt. This can be fixed by
clearing the I-bit in interruptable ISRs.</td>
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<td height=40 class=xl73 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit,
allowing them to be persistently set by interrupts. The lower four flag bits
are always restored.</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
<td class=xl76 style='border-top:none;border-left:none'>8-bit Data</td>
<td class=xl103 style='border-top:none;border-left:none'>x"FF"</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
<td class=xl73 style='border-top:none;border-left:none'>Real</td>
<td class=xl74 style='border-top:none;border-left:none'>-</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
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