Subversion Repositories open8_urisc

-- Copyright (c)2023 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
--       notice, this list of conditions and the following disclaimer in the
--       documentation and/or other materials provided with the distribution,
--       where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL units : o8_de0_nano_adc_if
-- Description: Stitches together all of the components needed to supply data
--               from the DE0 nano's on-board ADC. Provides an interrupt output
--               when the 8th (last) input is written to the buffer.
--
-- Register Map:
-- Offset  Bitfield Description                        Read/Write
--   0x00  AAAAAAAA AFE 0, Channel 0, Lower Byte          RO
--   0x01  AAAAAAAA AFE 0, Channel 0, Upper Byte          RO
--   0x02  AAAAAAAA AFE 0, Channel 1, Lower Byte          RO
--   0x03  AAAAAAAA AFE 0, Channel 1, Upper Byte          RO
--   0x04  AAAAAAAA AFE 0, Channel 2, Lower Byte          RO
--   0x05  AAAAAAAA AFE 0, Channel 2, Upper Byte          RO
--   0x06  AAAAAAAA AFE 0, Channel 3, Lower Byte          RO
--   0x07  AAAAAAAA AFE 0, Channel 3, Upper Byte          RO
--   0x08  AAAAAAAA AFE 0, Channel 4, Lower Byte          RO
--   0x09  AAAAAAAA AFE 0, Channel 4, Upper Byte          RO
--   0x0A  AAAAAAAA AFE 0, Channel 5, Lower Byte          RO
--   0x0B  AAAAAAAA AFE 0, Channel 5, Upper Byte          RO
--   0x0C  AAAAAAAA AFE 0, Channel 6, Lower Byte          RO
--   0x0D  AAAAAAAA AFE 0, Channel 6, Upper Byte          RO
--   0x0E  AAAAAAAA AFE 0, Channel 7, Lower Byte          RO
--   0x0F  AAAAAAAA AFE 0, Channel 7, Upper Byte          RO
--
-- Revision History
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/18/23 Initial Upload
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library work;
  use work.open8_pkg.all;
  use work.open8_cfg.all;
 
entity o8_de0_nano_adc_if is
generic(
  Address                    : ADDRESS_TYPE
);
port(
  -- Bus IF Interface
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic;
  -- ADC IF
  ADC_SDO                    : in  std_logic;
  ADC_SDI                    : out std_logic;
  ADC_SCLK                   : out std_logic;
  ADC_CSn                    : out std_logic
);
end entity;
 
architecture behave of o8_de0_nano_adc_if is
 
  -- Bus Interface Signals
 
  alias Clock                is Open8_Bus.Clock;
  alias Reset                is Open8_Bus.Reset;
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
  signal RAW_Channel         : std_logic_vector(2 downto 0)  := (others => '0');
  signal RAW_Data            : std_logic_vector(15 downto 0) := (others => '0');
  signal RAW_Valid           : std_logic := '0';
 
  signal AVG_Busy            : std_logic := '0';
 
  signal AVG_Channel         : std_logic_vector(2 downto 0)  := (others => '0');
  signal AVG_Data            : std_logic_vector(15 downto 0) := (others => '0');
  signal AVG_Valid           : std_logic := '0';
 
  alias  Buf_Wr_Ptr          is AVG_Channel;
  alias  Buf_Wr_Data         is AVG_Data;
  alias  Buf_Wr_Valid        is AVG_Valid;
 
  alias  Buf_Rd_Ptr          is Open8_Bus.Address(3 downto 0);
  signal Buf_Rd_Data         : std_logic_vector(7 downto 0) := (others => '0');
 
  constant LAST_ADDR         : std_logic_vector(2 downto 0)  := (others => '1');
  signal Last_Sample         : std_logic := '0';
 
  constant User_Addr         : std_logic_vector(15 downto 4) :=
                               Address(15 downto 4);
  alias Comp_Addr            is Open8_Bus.Address(15 downto 4);
 
  signal Addr_Match          : std_logic := '0';
  signal Rd_En               : std_logic := '0';
 
begin
 
-------------------------------------------------------------------------------
-- ADC0 - Interface
-------------------------------------------------------------------------------
 
  U_ADC0 : entity work.adc12s022
  generic map(
    Clock_Frequency          => Clock_Frequency,
    Reset_Level              => Reset_Level
  )
  port map(
    Clock                    => Clock,
    Reset                    => Reset,
    --
    RAW_Channel              => RAW_Channel,
    RAW_Data                 => RAW_Data,
    RAW_Valid                => RAW_Valid,
    --
    Busy_In                  => AVG_Busy,
    --
    SDO                      => ADC_SDO,
    SDI                      => ADC_SDI,
    SCLK                     => ADC_SCLK,
    CSn                      => ADC_CSn
  );
 
  U_AVG0 : entity work.mavg_8ch_16b_64d
  generic map(
    Reset_Level              => Reset_Level
  )
  port map(
    Clock                    => Clock,
    Reset                    => Reset,
    --
    RAW_Channel              => RAW_Channel,
    RAW_Data                 => RAW_Data,
    RAW_Valid                => RAW_Valid,
    --
    Busy_Out                 => AVG_Busy,
    --
    AVG_Channel              => AVG_Channel,
    AVG_Out                  => AVG_Data,
    AVG_Valid                => AVG_Valid,
    --
    Busy_In                  => '0'
  );
 
-------------------------------------------------------------------------------
-- Buffer Storage
-------------------------------------------------------------------------------
 
  U_DBUF : entity work.adc_buffer
  port map(
    clock                    => Clock,
    data                     => Buf_Wr_Data,
    rdaddress                => Buf_Rd_Ptr,
    wraddress                => Buf_Wr_Ptr,
    wren                     => Buf_Wr_Valid,
    q                        => Buf_Rd_Data
  );
 
  U_DMON : entity work.adc_monitor
  port map(
    address                  => Buf_Wr_Ptr,
    clock                    => Clock,
    data                     => Buf_Wr_Data,
    wren                     => Buf_Wr_Valid,
    q                        => open
  );
 
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
                                '0';
 
  Last_Sample                <= Buf_Wr_Valid when Buf_Wr_Ptr = LAST_ADDR else '0';
 
  RAM_proc: process( Reset, Clock )
  begin
    if( Reset = Reset_Level )then
      Interrupt              <= '0';
      Rd_En                  <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
    elsif( rising_edge(Clock) )then
      Interrupt              <= Last_Sample;
      Rd_En                  <= Addr_Match;
      Rd_Data                <= OPEN8_NULLBUS;
      if( Rd_En = '1' )then
        Rd_Data              <= Buf_Rd_Data;
      end if;
    end if;
  end process;
 
end architecture;