Subversion Repositories open8_urisc

-- Copyright (c)2023 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
--       notice, this list of conditions and the following disclaimer in the
--       documentation and/or other materials provided with the distribution,
--       where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units :  o8_romtape_8k
-- Description:  Provides serial FIFO-like access to an 8k ROM with settable
--            :   start address and increment. Automatically increments on
--            :   read.
--            :  This allows for bulk data to be accessed without using up
--            :   large amounts of address space, such as text strings or
--            :   configuration parameters.
--
--            :  Note 1: The ROM Position register tracks the internal
--            :   address, and will change once the ROM is accessed.
--
--            :  Note 2: The ROM Address Auto-Increment value is a signed
--            :   offset. This implies that the auto-increment varies from
--            :   -128 to 127.
--            :   A value of 0x00 will disable the auto-increment function.
 
-- WP Register Map:
-- Offset  Bitfield Description                        Read/Write
--   0x00  AAAAAAAA ROM Data                             (RO)
--   0x01  AAAAAAAA ROM Address Auto-Increment           (RW)
--   0x02  AAAAAAAA ROM Position (lower)                 (RW)
--   0x03  ---AAAAA ROM Position (upper)                 (RW)
--
-- Revision History
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
-- Seth Henry      07/18/23 Initial Design
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
 
library work;
  use work.open8_pkg.all;
 
entity o8_romtape_8k is
generic(
  Address                    : ADDRESS_TYPE
);
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE
);
end entity;
 
architecture behave of o8_romtape_8k is
 
  alias Clock                is Open8_Bus.Clock;
  alias Reset                is Open8_Bus.Reset;
 
  constant User_Addr         : std_logic_vector(15 downto 2)
                               := Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  signal Addr_Match          : std_logic;
 
  alias  Reg_Addr            is Open8_Bus.Address(1 downto 0);
  signal Reg_Sel             : std_logic_vector(1 downto 0);
 
  signal Wr_En               : std_logic := '0';
  signal Wr_Data             : DATA_TYPE := OPEN8_NULLBUS;
  signal Rd_En               : std_logic := '0';
 
  signal Address_Ptr         : signed(12 downto 0);
  alias  Address_Ptr_L       is Address_Ptr(7 downto 0);
  alias  Address_Ptr_H       is Address_Ptr(12 downto 8);
 
  signal Address_Incr        : signed(12 downto 0);
  alias  Address_Incr_L      is Address_Incr(7 downto 0);
  alias  Address_Incr_H      is Address_Incr(12 downto 8);
 
  constant DEFLT_INCR        : signed(12 downto 0) :=
                                 conv_signed(1,13);
 
  signal ROM_Ptr             : std_logic_vector(12 downto 0);
  signal ROM_Data            : std_logic_vector(7 downto 0);
 
begin
 
  -- Due to reads altering the state of the entity, all access should be
  --  qualified by Write_Qual
  Addr_Match                 <= Write_Qual when Comp_Addr = User_Addr else '0';
 
  Reg_proc: process( Reset, Clock )
  begin
    if( Reset = Reset_Level )then
 
      Address_Ptr            <= (others => '0');
      Address_Incr           <= DEFLT_INCR;
 
      Reg_Sel                <= (others => '0');
      Wr_En                  <= '0';
      Wr_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
    elsif( rising_edge(Clock) )then
      Reg_Sel                <= Reg_Addr;
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_Data                <= Open8_Bus.Wr_Data;
      if( Wr_en = '1' )then
        case( Reg_Sel )is
          when "01" =>
            Address_Incr_L   <= signed(Wr_Data);
            Address_Incr_H   <= (others => Wr_Data(7));
          when "10" =>
            Address_Ptr_L    <= signed(Wr_Data);
          when "11" =>
            Address_Ptr_H    <= signed(Wr_Data(4 downto 0));
          when others =>
            null;
        end case;
      end if;
 
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
 
      Rd_Data                <= OPEN8_NULLBUS;
      if( Rd_En = '1' )then
        case( Reg_Sel )is
          when "00" =>
            Rd_Data          <= ROM_Data;
            Address_Ptr      <= Address_Ptr + Address_Incr;
          when "01" =>
            Rd_Data          <= std_logic_vector(Address_Incr_L);
          when "10" =>
            Rd_Data          <= ROM_Ptr(7 downto 0);
          when "11" =>
            Rd_Data          <= "000" & ROM_Ptr(12 downto 8);
          when others =>
            null;
        end case;
      end if;
 
    end if;
  end process;
 
  ROM_Ptr                    <= std_logic_vector(Address_Ptr);
 
  U_ROM : entity work.rom_8k_core
  port map(
    address                  => ROM_Ptr,
    clock                    => Clock,
    q                        => ROM_Data
  );
 
end architecture;