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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_timer24.vhd] - Rev 321
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-- VHDL Units : o8_timer24 -- Description: Provides an 24-bit microsecond resolution timer for generating -- : periodic interrupts for the Open8 CPU. This timer has a -- : programmable timebase selector that allows the resolution to -- : be set at run-time. -- -- Register Map: -- Offset Bitfield Description Read/Write -- 0x00 AAAAAAAA Req Interval Byte 0 (RW) -- 0x01 AAAAAAAA Req Interval Byte 1 (RW) -- 0x02 AAAAAAAA Req Interval Byte 2 (RW) -- 0x03 CBA----- Control/Status Register (RW) -- A: Update timer (WR) or pending (RD) -- B: Timebase (0 = uS / 1 = mS) -- C: Output Enable -- -- Notes : Setting the output to 0x000000 OR clearing bit C will disable -- : the timer. -- : Update pending is true if bit A is 1, otherwise false -- -- Revision History -- Author Date Change ------------------ -------- --------------------------------------------------- -- Seth Henry 05/17/23 Initial upload (based on sys_timer_ii) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; library work; use work.open8_pkg.all; entity o8_timer24 is generic( Address : ADDRESS_TYPE ); port( Open8_Bus : in OPEN8_BUS_TYPE; Write_Qual : in std_logic := '1'; Rd_Data : out DATA_TYPE; Interrupt : out std_logic ); end entity; architecture behave of o8_timer24 is alias Clock is Open8_Bus.Clock; alias Reset is Open8_Bus.Reset; alias uSec_Tick is Open8_Bus.uSec_Tick; constant User_Addr : std_logic_vector(15 downto 2) := Address(15 downto 2); alias Comp_Addr is Open8_Bus.Address(15 downto 2); signal Addr_Match : std_logic := '0'; alias Reg_Sel_d is Open8_Bus.Address(1 downto 0); signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00"; signal Wr_En_d : std_logic; signal Wr_En_q : std_logic := '0'; alias Wr_Data_d is Open8_Bus.Wr_Data; signal Wr_Data_q : DATA_TYPE := x"00"; signal Rd_En_d : std_logic := '0'; signal Rd_En_q : std_logic := '0'; signal Req_Interval : std_logic_vector(23 downto 0) := x"000000"; alias Req_Interval_B0 is Req_Interval( 7 downto 0); alias Req_Interval_B1 is Req_Interval(15 downto 8); alias Req_Interval_B2 is Req_Interval(23 downto 16); signal Int_Interval : std_logic_vector(23 downto 0) := x"000000"; signal Timebase : std_logic := '0'; signal Update_Interval : std_logic := '0'; signal Update_Pending : std_logic := '0'; signal Output_Enable : std_logic := '0'; signal Output_Qual : std_logic := '0'; signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000"; constant MSEC_DELAY : std_logic_vector(9 downto 0) := conv_std_logic_vector(1000,10); signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0'); signal mSec_Tick : std_logic := '0'; signal Timer_Tick : std_logic := '0'; begin Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; Wr_En_d <= Addr_Match and Open8_Bus.Wr_En; Rd_En_d <= Addr_Match and Open8_Bus.Rd_En; mSec_Tick_proc: process( Clock, Reset ) begin if( Reset = Reset_Level )then mSec_Timer <= (others => '0'); mSec_Tick <= '0'; elsif( rising_edge(Clock) )then mSec_Timer <= mSec_Timer - uSec_Tick; mSec_Tick <= '0'; if( mSec_Timer = 0 )then mSec_Timer <= MSEC_DELAY; mSec_Tick <= '1'; end if; end if; end process; Timer_Tick <= mSec_Tick when Timebase = '1' else uSec_Tick; io_reg: process( Clock, Reset ) begin if( Reset = Reset_Level )then Reg_Sel_q <= "00"; Wr_En_q <= '0'; Wr_Data_q <= x"00"; Rd_En_q <= '0'; Rd_Data <= OPEN8_NULLBUS; Req_Interval <= x"000000"; Update_Interval <= '0'; Update_Pending <= '0'; Timebase <= '0'; Output_Enable <= '0'; elsif( rising_edge( Clock ) )then Reg_Sel_q <= Reg_Sel_d; Wr_En_q <= Wr_En_d; Wr_Data_q <= Wr_Data_d; Update_Interval <= '0'; if( Wr_En_q = '1' and Write_Qual = '1' )then case( Reg_Sel_q )is when "00" => Req_Interval_B0 <= Wr_Data_q; Update_Pending <= '1'; when "01" => Req_Interval_B1 <= Wr_Data_q; Update_Pending <= '1'; when "10" => Req_Interval_B2 <= Wr_Data_q; Update_Pending <= '1'; when "11" => Output_Enable <= Wr_Data_q(7); Timebase <= Wr_Data_q(6); Update_Interval <= Wr_Data_q(5); when others => null; end case; end if; if( Update_Interval = '1' )then Update_Pending <= '0'; end if; Rd_Data <= OPEN8_NULLBUS; Rd_En_q <= Rd_En_d; if( Rd_En_q = '1' )then case( Reg_Sel_q )is when "00" => Rd_Data <= Req_Interval_B0; when "01" => Rd_Data <= Req_Interval_B1; when "10" => Rd_Data <= Req_Interval_B2; when "11" => Rd_Data <= Output_Enable & Timebase & Update_Pending & "00000"; when others => null; end case; end if; end if; end process; Interval_proc: process( Clock, Reset ) begin if( Reset = Reset_Level )then Output_Qual <= '0'; Int_Interval <= x"000000"; Timer_Cnt <= x"000000"; Interrupt <= '0'; elsif( rising_edge(Clock) )then Output_Qual <= Output_Enable and or_reduce(Int_Interval); Interrupt <= '0'; Timer_Cnt <= Timer_Cnt - Timer_Tick; if( Update_Interval = '1' )then Int_Interval <= Req_Interval; Timer_Cnt <= Req_Interval; elsif( or_reduce(Timer_Cnt) = '0' )then Timer_Cnt <= Int_Interval; Interrupt <= Output_Qual; end if; end if; end process; end architecture;
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