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[/] [open8_urisc/] [trunk/] [VHDL/] [status_led.vhd] - Rev 271

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-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
--       notice, this list of conditions and the following disclaimer in the
--       documentation and/or other materials provided with the distribution,
--       where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units :  status_led
-- Description:  Provides a multi-state status LED controller
--
-- LED Modes:
-- 0x0 - LED is fully off
-- 0x1 - LED is fully on
-- 0x2 - LED is dimmed to 50%
-- 0x3 - LED Toggles at 1Hz
-- 0x4 - LED fades in and out
--
-- Revision History
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/24/20 Created as a separate sub-component
 
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_misc.all;
 
entity status_led is
generic(
  Reset_Level                : std_logic
);
port(
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  LED_Mode                   : in  std_logic_vector(2 downto 0);
  LED_Out                    : out std_logic
);
end entity;
 
architecture behave of status_led is
 
  --  hold the supplied integer.
  function ceil_log2 (x : in natural) return natural is
    variable retval          : natural;
  begin
    retval                   := 1;
    while ((2**retval) - 1) < x loop
      retval                 := retval + 1;
    end loop;
    return retval;
  end function;
 
  signal Dim50Pct_Out        : std_logic := '0';
 
  constant TAP1              : integer := 16;
  constant TAP2              : integer := 21;
  constant TAP3              : integer := 22;
  constant TAP4              : integer := 23;
 
  constant Init_Seed         : std_logic_vector(23 downto 0) := x"000001";
 
  signal d0                  : std_logic := '0';
  signal LFSR_poly           : std_logic_vector(23 downto 0) := (others => '0');
 
  signal Cycle_Toggle        : std_logic;
 
  constant TIMER_MSB         : integer range 9 to 20 := 18;
 
  signal Fade_Timer1         : std_logic_vector(TIMER_MSB downto 0) :=
                                (others => '0');
  signal Fade_Timer2         : std_logic_vector(TIMER_MSB downto 0) :=
                                (others => '0');
  signal Fade_Out            : std_logic := '0';
 
begin
 
  Output_FF: process( Clock, Reset )
  begin
    if( Reset = Reset_Level )then
      LED_Out                <= '0';
    elsif( rising_edge(Clock) )then
      LED_Out                <= '0';
      case( LED_Mode )is
        when "001" =>
          LED_Out            <= '1';
        when "010" =>
          LED_Out            <= Dim50Pct_Out;
        when "011" =>
          LED_Out            <= Cycle_Toggle;
        when "100" =>
          LED_Out            <= Fade_out;
        when others => null;
      end case;
    end if;
  end process;
 
  d0                         <= LFSR_poly(TAP4) xnor LFSR_poly(TAP3) xnor
                                LFSR_poly(TAP2) xnor LFSR_poly(TAP1);
 
  Timer_proc: process( Clock, Reset )
  begin
    if( Reset = Reset_Level )then
      Dim50Pct_Out           <= '0';
      LFSR_poly              <= Init_Seed;
      Cycle_Toggle           <= '0';
      Fade_Timer1            <= (others => '0');
      Fade_Timer2            <= (others => '0');
      Fade_out               <= '0';
    elsif( rising_edge(Clock) )then
      Dim50Pct_Out           <= not Dim50Pct_Out;
 
      LFSR_poly              <= LFSR_poly(22 downto 0) & d0;
      if( LFSR_poly = Init_Seed )then
        Cycle_Toggle         <= not Cycle_Toggle;
      end if;
 
      Fade_Timer1            <= Fade_Timer1 - 1;
      Fade_Timer2            <= Fade_Timer2 - 1;
      if( or_reduce(Fade_Timer2) = '0' )then
        Fade_Timer2(TIMER_MSB downto TIMER_MSB - 8) <= (others => '1');
        Fade_Timer2(TIMER_MSB - 9 downto 0 )        <= (others => '0');
      end if;
      Fade_out               <= Fade_Timer1(TIMER_MSB) xor
                                Fade_Timer2(TIMER_MSB);
    end if;
  end process;
 
end architecture;
 

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