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2011-05-31 Paul Brook <paul@codesourcery.com>* opcode/arm.h (ARM_ARCH_V7R_IDIV): Define.2011-04-18 Julian Brown <julian@codesourcery.com>* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.2011-04-11 Dan McDonald <dan@wellkeeper.com>PR gas/12296* arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):New instruction set flags.(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>* mips.h (M_PREF_AB): New enum value.2011-02-12 Mike Frysinger <vapier@gentoo.org>* bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,M_IU): Define.(is_macmod_pmove, is_macmod_hmove): New functions.2011-02-11 Mike Frysinger <vapier@gentoo.org>* bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.2011-02-04 Bernd Schmidt <bernds@codesourcery.com>* tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.* tic6x.h (TIC6X_INSN_ATOMIC): Remove.2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>PR gas/11395* hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit"bb" entries.2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>PR gas/11395* hppa.h: Clear "d" bit in "add" and "sub" patterns.2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>* mips.h: Update commentary after last commit.2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>* mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)(OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)(INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>* mips.h: Fix previous commit.2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>* mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.(INSN_LOONGSON_3A): Clear bit 31.2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>PR gas/12198* arm.h (ARM_AEXT_V6M_ONLY): New define.(ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.(ARM_ARCH_V6M_ONLY): New define.2010-11-11 Mingming Sun <mingm.sun@gmail.com>* mips.h (INSN_LOONGSON_3A): Defined.(CPU_LOONGSON_3A): Defined.(OPCODE_IS_MEMBER): Add LOONGSON_3A.2010-10-09 Matt Rice <ratmice@gmail.com>* cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.(CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>* arm.h (ARM_EXT_VIRT): New define.(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include VirtualizationExtensions.2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>* arm.h (ARM_AEXT_ADIV): New define.(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>* arm.h (ARM_EXT_OS): New define.(ARM_AEXT_V6SM): Likewise.(ARM_ARCH_V6SM): Likewise.2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>* arm.h (ARM_EXT_MP): Add.(ARM_ARCH_V7A_MP): Likewise.2010-09-22 Mike Frysinger <vapier@gentoo.org>* bfin.h: Declare pseudoChr structs/defines.2010-09-21 Mike Frysinger <vapier@gentoo.org>* bfin.h: Strip trailing whitespace.2010-07-29 DJ Delorie <dj@redhat.com>* rx.h (RX_Operand_Type): Add TwoReg.(RX_Opcode_ID): Remove ediv and ediv2.2010-07-27 DJ Delorie <dj@redhat.com>* rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>Ina Pandit <ina.pandit@kpitcummins.com>* v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 andPROCESSOR_V850E2_ALL.Remove PROCESSOR_V850EA support.(v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG andV850_OPERAND_PERCENT.Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX andV850_NOT_R0.Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISPand V850E_PUSH_POP2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.(MIPS16_INSN_BRANCH): Rename to...(MIPS16_INSN_COND_BRANCH): ... this.2010-07-03 Alan Modra <amodra@gmail.com>* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.Renumber other PPC_OPCODE defines.2010-07-03 Alan Modra <amodra@gmail.com>* ppc.h (PPC_OPCODE_COMMON): Expand comment.2010-06-29 Alan Modra <amodra@gmail.com>* maxq.h: Delete file.2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>* ppc.h (PPC_OPCODE_E500): Define.2010-05-26 Catherine Moore <clm@codesourcery.com>* opcode/mips.h (INSN_MIPS16): Remove.2010-04-21 Joseph Myers <joseph@codesourcery.com>* tic6x-insn-formats.h (s_branch): Correct typo in bitmask.2010-04-15 Nick Clifton <nickc@redhat.com>* alpha.h: Update copyright notice to use GPLv3.* arc.h: Likewise.* arm.h: Likewise.* avr.h: Likewise.* bfin.h: Likewise.* cgen.h: Likewise.* convex.h: Likewise.* cr16.h: Likewise.* cris.h: Likewise.* crx.h: Likewise.* d10v.h: Likewise.* d30v.h: Likewise.* dlx.h: Likewise.* h8300.h: Likewise.* hppa.h: Likewise.* i370.h: Likewise.* i386.h: Likewise.* i860.h: Likewise.* i960.h: Likewise.* ia64.h: Likewise.* m68hc11.h: Likewise.* m68k.h: Likewise.* m88k.h: Likewise.* maxq.h: Likewise.* mips.h: Likewise.* mmix.h: Likewise.* mn10200.h: Likewise.* mn10300.h: Likewise.* msp430.h: Likewise.* np1.h: Likewise.* ns32k.h: Likewise.* or32.h: Likewise.* pdp11.h: Likewise.* pj.h: Likewise.* pn.h: Likewise.* ppc.h: Likewise.* pyr.h: Likewise.* rx.h: Likewise.* s390.h: Likewise.* score-datadep.h: Likewise.* score-inst.h: Likewise.* sparc.h: Likewise.* spu-insns.h: Likewise.* spu.h: Likewise.* tic30.h: Likewise.* tic4x.h: Likewise.* tic54x.h: Likewise.* tic80.h: Likewise.* v850.h: Likewise.* vax.h: Likewise.2010-03-25 Joseph Myers <joseph@codesourcery.com>* tic6x-control-registers.h, tic6x-insn-formats.h,tic6x-opcode-table.h, tic6x.h: New.2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>* mips.h: (LOONGSON2F_NOP_INSN): New macro.2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>* opcode/ppc.h (PPC_OPCODE_TITAN): Define.2010-01-14 H.J. Lu <hongjiu.lu@intel.com>* ia64.h (ia64_find_opcode): Remove argument name.(ia64_find_next_opcode): Likewise.(ia64_dis_opcode): Likewise.(ia64_free_opcode): Likewise.(ia64_find_dependency): Likewise.2009-11-22 Doug Evans <dje@sebabeach.org>* cgen.h: Include bfd_stdint.h.(CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.2009-11-18 Paul Brook <paul@codesourcery.com>* arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.2009-11-17 Paul Brook <paul@codesourcery.com>Daniel Jacobowitz <dan@codesourcery.com>* arm.h (ARM_EXT_V6_DSP): Define.(ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.(ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.2009-11-04 DJ Delorie <dj@redhat.com>* rx.h (rx_decode_opcode) (mvtipl): Add.(mvtcp, mvfcp, opecp): Remove.2009-11-02 Paul Brook <paul@codesourcery.com>* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,FPU_ARCH_NEON_VFP_V4): Define.2009-10-23 Doug Evans <dje@sebabeach.org>* cgen-bitset.h: Delete, moved to ../cgen/bitset.h.* cgen.h: Update. Improve multi-inclusion macro name.2009-10-02 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (PPC_OPCODE_476): Define.2009-10-01 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.2009-09-29 DJ Delorie <dj@redhat.com>* rx.h: New file.2009-09-22 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (ppc_cpu_t): Typedef to uint64_t.2009-09-21 Ben Elliston <bje@au.ibm.com>* ppc.h (PPC_OPCODE_PPCA2): New.2009-09-05 Martin Thuresson <martin@mtme.org>* ia64.h (struct ia64_operand): Renamed member class to op_class.2009-08-29 Martin Thuresson <martin@mtme.org>* tic30.h (template): Rename type template toinsn_template. Updated code to use new name.* tic54x.h (template): Rename type template toinsn_template.2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>* hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.2009-06-11 Anthony Green <green@moxielogic.com>* moxie.h (MOXIE_F3_PCREL): Define.(moxie_form3_opc_info): Grow.2009-06-06 Anthony Green <green@moxielogic.com>* moxie.h (MOXIE_F1_M): Define.2009-04-15 Anthony Green <green@moxielogic.com>* moxie.h: Created.2009-04-06 DJ Delorie <dj@redhat.com>* h8300.h: Add relaxation attributes to MOVA opcodes.2009-03-10 Alan Modra <amodra@bigpond.net.au>* ppc.h (ppc_parse_cpu): Declare.2009-03-02 Qinwei <qinwei@sunnorth.com.cn>* score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5and _IMM11 for mbitclr and mbitset.* score-datadep.h: Update dependency information.2009-02-26 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (PPC_OPCODE_POWER7): New.2009-02-06 Doug Evans <dje@google.com>* i386.h: Add comment regarding sse* insns and prefixes.2009-02-03 Sandip Matte <sandip@rmicorp.com>* mips.h (INSN_XLR): Define.(INSN_CHIP_MASK): Update.(CPU_XLR): Define.(OPCODE_IS_MEMBER): Update.(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.2009-01-28 Doug Evans <dje@google.com>* opcode/i386.h: Add multiple inclusion protection.(EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)(EDI_REG_NUM): New macros.(MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.(SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.(REX_PREFIX_P): New macro.2009-01-09 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (struct powerpc_opcode): New field "deprecated".(PPC_OPCODE_NOPOWER4): Delete.2008-11-28 Joshua Kinard <kumba@gentoo.org>* mips.h: Define CPU_R14000, CPU_R16000.(OPCODE_IS_MEMBER): Include R14000, R16000 in test.2008-11-18 Catherine Moore <clm@codesourcery.com>* arm.h (FPU_NEON_FP16): New.(FPU_ARCH_NEON_FP16): New.2008-11-06 Chao-ying Fu <fu@mips.com>* mips.h: Doucument '1' for 5-bit sync type.2008-08-28 H.J. Lu <hongjiu.lu@intel.com>* ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. UpdateIA64_RS_CR.2008-08-01 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.2008-07-30 Michael J. Eager <eager@eagercon.com>* ppc.h (PPC_OPCODE_405): Define.(PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.2008-06-13 Peter Bergner <bergner@vnet.ibm.com>* ppc.h (ppc_cpu_t): New typedef.(struct powerpc_opcode <flags>): Use it.(struct powerpc_operand <insert, extract>): Likewise.(struct powerpc_macro <flags>): Likewise.2008-06-12 Adam Nemet <anemet@caviumnetworks.com>* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.Update comment before MIPS16 field descriptors to mention MIPS16.(OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count forBBIT.(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):New bit masks and shift counts for cins and exts.* mips.h: Document new field descriptors +Q.(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.2008-04-28 Adam Nemet <anemet@caviumnetworks.com>* mips.h (INSN_MACRO): Move it up to the the pinfo macros.(INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.2008-04-14 Edmar Wienskoski <edmar@freescale.com>* ppc.h: (PPC_OPCODE_E500MC): New.2008-04-03 H.J. Lu <hongjiu.lu@intel.com>* i386.h (MAX_OPERANDS): Set to 5.(MAX_MNEM_SIZE): Changed to 20.2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>* avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.2008-03-09 Paul Brook <paul@codesourcery.com>* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.2008-03-04 Paul Brook <paul@codesourcery.com>* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>Nick Clifton <nickc@redhat.com>PR 3134* h8300.h (h8_opcodes): Add an encoding for a mov.l instructionwith a 32-bit displacement but without the top bit of the 4th byteset.2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>* cr16.h (cr16_num_optab): Declared.2008-02-14 Hakan Ardo <hakan@debian.org>PR gas/2626* avr.h (AVR_ISA_2xxe): Define.2008-02-04 Adam Nemet <anemet@caviumnetworks.com>* mips.h: Update copyright.(INSN_CHIP_MASK): New macro.(INSN_OCTEON): New macro.(CPU_OCTEON): New macro.(OPCODE_IS_MEMBER): Handle Octeon instructions.2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>* avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>* avr.h (AVR_ISA_USB162): Add new opcode set.(AVR_ISA_AVR3): Likewise.2007-11-29 Mark Shinwell <shinwell@codesourcery.com>* mips.h (INSN_LOONGSON_2E): New.(INSN_LOONGSON_2F): New.(CPU_LOONGSON_2E): New.(CPU_LOONGSON_2F): New.(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.2007-11-29 Mark Shinwell <shinwell@codesourcery.com>* mips.h (INSN_ISA*): Redefine certain values as anenumeration. Update comments.(mips_isa_table): New.(ISA_MIPS*): Redefine to match enumeration.(OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*values.2007-08-08 Ben Elliston <bje@au.ibm.com>* ppc.h (PPC_OPCODE_PPCPS): New.2007-07-03 Nathan Sidwell <nathan@codesourcery.com>* m68k.h: Document j K & E.2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>* cr16.h: New file for CR16 target.2007-05-02 Alan Modra <amodra@bigpond.net.au>* ppc.h (PPC_OPERAND_PLUS1): Update comment.2007-04-23 Nathan Sidwell <nathan@codesourcery.com>* m68k.h (mcfisa_c): New.(mcfusp, mcf_mask): Adjust.2007-04-20 Alan Modra <amodra@bigpond.net.au>* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".(num_powerpc_operands): Declare.(PPC_OPERAND_SIGNED et al): Redefine as hex.(PPC_OPERAND_PLUS1): Define.2007-03-21 H.J. Lu <hongjiu.lu@intel.com>* i386.h (REX_MODE64): Renamed to ...(REX_W): This.(REX_EXTX): Renamed to ...(REX_R): This.(REX_EXTY): Renamed to ...(REX_X): This.(REX_EXTZ): Renamed to ...(REX_B): This.2007-03-15 H.J. Lu <hongjiu.lu@intel.com>* i386.h: Add entries from config/tc-i386.h and move tablesto opcodes/i386-opc.h.2007-03-13 H.J. Lu <hongjiu.lu@intel.com>* i386.h (FloatDR): Removed.(i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.2007-03-01 Alan Modra <amodra@bigpond.net.au>* spu-insns.h: Add soma double-float insns.2007-02-20 Thiemo Seufer <ths@mips.com>Chao-Ying Fu <fu@mips.com>* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.(INSN_DSPR2): Add flag for DSP R2 instructions.(M_BALIGN): New macro.2007-02-14 Alan Modra <amodra@bigpond.net.au>* i386.h (i386_optab): Replace all occurrences of Seg2ShortFormand Seg3ShortFrom with Shortform.2007-02-11 H.J. Lu <hongjiu.lu@intel.com>PR gas/4027* i386.h (i386_optab): Put the real "test" before the pseudoone.2007-01-08 Kazu Hirata <kazu@codesourcery.com>* m68k.h (m68010up): OR fido_a.2006-12-25 Kazu Hirata <kazu@codesourcery.com>* m68k.h (fido_a): New.2006-12-24 Kazu Hirata <kazu@codesourcery.com>* m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the definedvalues.2006-11-08 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>* score-inst.h (enum score_insn_type): Add Insn_internal.2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>Yukishige Shibata <shibata@rd.scei.sony.co.jp>Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>Alan Modra <amodra@bigpond.net.au>* spu-insns.h: New file.* spu.h: New file.2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>* ppc.h (PPC_OPCODE_CELL): Define.2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>* i386.h : Modify opcode to support for the change in POPCNT opcodein amdfam10 architecture.2006-09-28 H.J. Lu <hongjiu.lu@intel.com>* i386.h: Replace CpuMNI with CpuSSSE3.2006-09-26 Mark Shinwell <shinwell@codesourcery.com>Joseph Myers <joseph@codesourcery.com>Ian Lance Taylor <ian@wasabisystems.com>Ben Elliston <bje@wasabisystems.com>* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>* score-datadep.h: New file.* score-inst.h: New file.2006-07-14 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,movdq2q and movq2dq.2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>Michael Meissner <michael.meissner@amd.com>* i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).2006-06-12 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Add "nop" with memory reference.2006-06-12 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Update comment for 64bit NOP.2006-06-06 Ben Elliston <bje@au.ibm.com>Anton Blanchard <anton@samba.org>* ppc.h (PPC_OPCODE_POWER6): Define.Adjust whitespace.2006-06-05 Thiemo Seufer <ths@mips.com>* mips.h: Improve description of MT flags.2006-05-25 Richard Sandiford <richard@codesourcery.com>* m68k.h (mcf_mask): Define.2006-05-05 Thiemo Seufer <ths@mips.com>David Ung <davidu@mips.com>* mips.h (enum): Add macro M_CACHE_AB.2006-05-04 Thiemo Seufer <ths@mips.com>Nigel Stephens <nigel@mips.com>David Ung <davidu@mips.com>* mips.h: Add INSN_SMARTMIPS define.2006-04-30 Thiemo Seufer <ths@mips.com>David Ung <davidu@mips.com>* mips.h: Defines udi bits and masks. Add description ofcharacters which may appear in the args field of udiinstructions.2006-04-26 Thiemo Seufer <ths@networkno.de>* mips.h: Improve comments describing the bitfield instructionfields.2006-04-26 Julian Brown <julian@codesourcery.com>* arm.h (FPU_VFP_EXT_V3): Define constant.(FPU_NEON_EXT_V1): Likewise.(FPU_VFP_HARD): Update.(FPU_VFP_V3): Define macro.(FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>* avr.h (AVR_ISA_PWMx): New.2006-03-28 Nathan Sidwell <nathan@codesourcery.com>* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.2006-03-10 Paul Brook <paul@codesourcery.com>* arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes comefirst. Correct mask of bb "B" opcode.2006-02-27 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Support Intel Merom New Instructions.2006-02-24 Paul Brook <paul@codesourcery.com>* arm.h: Add V7 feature bits.2006-02-23 H.J. Lu <hongjiu.lu@intel.com>* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.2006-01-31 Paul Brook <paul@codesourcery.com>Richard Earnshaw <rearnsha@arm.com>* arm.h: Use ARM_CPU_FEATURE.(ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.(arm_feature_set): Change to a structure.(ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,ARM_FEATURE): New macros.2005-12-07 Hans-Peter Nilsson <hp@axis.com>* cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)(MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.(ADD_PC_INCR_OPCODE): Don't define.2005-12-06 H.J. Lu <hongjiu.lu@intel.com>PR gas/1874* i386.h (i386_optab): Add 64bit support for monitor and mwait.2005-11-14 David Ung <davidu@mips.com>* mips.h: Assign 'm'/'M' codes to MIPS16e save/restoreinstructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS forsave/restore encoding of the args field.2005-10-28 Dave Brolley <brolley@redhat.com>Contribute the following changes:2005-02-16 Dave Brolley <brolley@redhat.com>* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Renamecgen_isa_mask_* to cgen_bitset_*.* cgen.h: Likewise.2003-10-21 Richard Sandiford <rsandifo@redhat.com>* cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.(CGEN_ATTR_ENTRY): Change "value" to type "unsigned".(CGEN_CPU_TABLE): Make isas a ponter.2003-09-29 Dave Brolley <brolley@redhat.com>* cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.(CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.(CGEN_ATTR_VALUE_TYPE): Use these new typedefs.2002-12-13 Dave Brolley <brolley@redhat.com>* cgen.h (symcat.h): #include it.(cgen-bitset.h): #include it.(CGEN_ATTR_VALUE_TYPE): Now a union.(CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.(CGEN_ATTR_ENTRY): 'value' now unsigned.(cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).* cgen-bitset.h: New file.2005-09-30 Catherine Moore <clm@cm00re.com>* bfin.h: New file.2005-10-24 Jan Beulich <jbeulich@novell.com>* ia64.h (enum ia64_opnd): Move memory operand out of set ofindirect operands.2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.Add FLAG_STRICT to pa10 ftest opcode.2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (pa_opcodes): Remove lha entries.2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (FLAG_STRICT): Revise comment.(pa_opcode): Revise ordering rules. Add/move strict pa10 variantsbefore corresponding pa11 opcodes. Add strict pa10 register-immediateentries for "fdc".2005-09-30 Catherine Moore <clm@cm00re.com>* bfin.h: New file.2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.2005-09-06 Chao-ying Fu <fu@mips.com>* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): Newdefine.Document !, $, *, &, g, +t, +T operand formats for MT instructions.(INSN_ASE_MASK): Update to include INSN_MT.(INSN_MT): New define for MT ASE.2005-08-25 Chao-ying Fu <fu@mips.com>* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSPinstructions.(INSN_DSP): New define for DSP ASE.2005-08-18 Alan Modra <amodra@bigpond.net.au>* a29k.h: Delete.2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>* ppc.h (PPC_OPCODE_E300): Define.2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>PR gas/336* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlband pitlb.2005-07-27 Jan Beulich <jbeulich@novell.com>* i386.h (i386_optab): Add comment to movd. Use LongMem for allmovd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.Add movq-s as 64-bit variants of movd-s.2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h: Fix punctuation in comment.* hppa.h (pa_opcode): Add rules for opcode ordering. Check first forimplicit space-register addressing. Set space-register bits on opcodesusing implicit space-register addressing. Add various missing pa20long-immediate opcodes. Remove various opcodes using implicit 3-bitspace-register addressing. Use "fE" instead of "fe" in variousfstw opcodes.2005-07-18 Jan Beulich <jbeulich@novell.com>* i386.h (i386_optab): Operands of aam and aad are unsigned.2007-07-15 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Support Intel VMX Instructions.2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.2005-07-05 Jan Beulich <jbeulich@novell.com>* i386.h (i386_optab): Add new insns.2005-07-01 Nick Clifton <nickc@redhat.com>* sparc.h: Add typedefs to structure declarations.2005-06-20 H.J. Lu <hongjiu.lu@intel.com>PR 1013* i386.h (i386_optab): Update comments for 64bit addressing onmov. Allow 64bit addressing for mov and movq.2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,respectively, in various floating-point load and store patterns.2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>* hppa.h (FLAG_STRICT): Correct comment.(pa_opcodes): Update load and store entries to allow both PA 1.X andPA 2.0 mneumonics when equivalent. Entries with cache controlcompleters now require PA 1.1. Adjust whitespace.2005-05-19 Anton Blanchard <anton@samba.org>* ppc.h (PPC_OPCODE_POWER5): Define.2005-05-10 Nick Clifton <nickc@redhat.com>* Update the address and phone number of the FSF organization inthe GPL notices in the following files:a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,tic54x.h, tic80.h, v850.h, vax.h2005-05-09 Jan Beulich <jbeulich@novell.com>* i386.h (i386_optab): Add ht and hnt.2005-04-18 Mark Kettenis <kettenis@gnu.org>* i386.h: Insert hyphens into selected VIA PadLock extensions.Add xcrypt-ctr. Provide aliases without hyphens.2005-04-13 H.J. Lu <hongjiu.lu@intel.com>Moved from ../ChangeLog2005-04-12 Paul Brook <paul@codesourcery.com>* m88k.h: Rename psr macros to avoid conflicts.2005-03-12 Zack Weinberg <zack@codesourcery.com>* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,and ARM_ARCH_V6ZKT2.2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.Remove redundant instruction types.(struct argument): X_op - new field.(struct cst4_entry): Remove.(no_op_insn): Declare.2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>* crx.h (enum argtype): Rename types, remove unused types.2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.(enum operand_type): Rearrange operands, edit comments.replace us<N> with ui<N> for unsigned immediate.replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escapeddisplacements (respectively).replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.(instruction type): Add NO_TYPE_INS.(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.(operand_entry): New field - 'flags'.(operand flags): New.2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>* crx.h (operand_type): Remove redundant types i3, i4,i5, i8, i12.Add new unsigned immediate types us3, us4, us5, us16.2005-04-12 Mark Kettenis <kettenis@gnu.org>* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt andadjust them accordingly.2005-04-01 Jan Beulich <jbeulich@novell.com>* i386.h (i386_optab): Add rdtscp.2005-03-29 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Don't allow the `l' suffix for movingbetween memory and segment register. Allow movq for moving betweengeneral-purpose register and segment register.2005-02-09 Jan Beulich <jbeulich@novell.com>PR gas/707* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf andFloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw andfnstsw.2006-02-07 Nathan Sidwell <nathan@codesourcery.com>* m68k.h (m68008, m68ec030, m68882): Remove.(m68k_mask): New.(cpu_m68k, cpu_cf): New.(mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.2005-01-25 Alexandre Oliva <aoliva@redhat.com>2004-11-10 Alexandre Oliva <aoliva@redhat.com>* cgen.h (enum cgen_parse_operand_type): AddCGEN_PARSE_OPERAND_SYMBOLIC.2005-01-21 Fred Fish <fnf@specifixinc.com>* mips.h: Change INSN_ALIAS to INSN2_ALIAS.Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.2005-01-19 Fred Fish <fnf@specifixinc.com>* mips.h (struct mips_opcode): Add new pinfo2 member.(INSN_ALIAS): New define for opcode table entries that arespecific instances of another entry, such as 'move' for an 'or'with a zero operand.(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>* mips.h (CPU_RM9000): Define.(OPCODE_IS_MEMBER): Handle CPU_RM9000.2004-11-25 Jan Beulich <jbeulich@novell.com>* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Movesto/from test registers are illegal in 64-bit mode. Add missingNoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix(previously one had to explicitly encode a rex64 prefix). Re-enablelahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppingssupport it there. Add cmpxchg16b as per Intel's 64-bit documentation.2004-11-23 Jan Beulich <jbeulich@novell.com>* i386.h (i386_optab): paddq and psubq, even in their MMX form, areavailable only with SSE2. Change the MMX additions introduced by SSEand 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!Ainstructions by their now designated identifier (since combining i686and 3DNow! does not really imply 3DNow!A).2004-11-19 Alan Modra <amodra@bigpond.net.au>* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>Vineet Sharma <vineets@noida.hcltech.com>* maxq.h: New file: Disassembly information for the maxq port.2004-11-05 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Put back "movzb".2004-11-04 Hans-Peter Nilsson <hp@axis.com>* cris.h (enum cris_insn_version_usage): Tweak formatting andcomments. Remove member cris_ver_sim. Add memberscris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.(struct cris_support_reg, struct cris_cond15): New types.(cris_conds15): Declare.(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.(NOP_Z_BITS): Define in terms of NOP_OPCODE.(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED andSIZE_FIELD_UNSIGNED.2004-11-04 Jan Beulich <jbeulich@novell.com>* i386.h (sldx_Suf): Remove.(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.(q_FP): Define, implying no REX64.(x_FP, sl_FP): Imply FloatMF.(i386_optab): Split reg and mem forms of moving from segment registersso that the memory forms can ignore the 16-/32-bit operand sizedistinction. Adjust a few others for Intel mode. Remove *FP uses fromall non-floating-point instructions. Unite 32- and 64-bit forms ofmovsx, movzx, and movd. Adjust floating point operations for the abovechanges to the *FP macros. Add DefaultSize to floating point controlinsns operating on larger memory ranges. Remove left over commentshinting at certain insns being Intel-syntax ones where the onesactually meant are already gone.2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>* crx.h: Add COPS_REG_INS - Coprocessor Special registerinstruction type.2004-09-30 Paul Brook <paul@codesourcery.com>* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.2004-09-11 Theodore A. Roth <troth@openavr.org>* avr.h: Add support foratmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.2004-08-24 Dmitry Diky <diwil@spec.ru>* msp430.h (msp430_opc): Add new instructions.(msp430_rcodes): Declare new instructions.(msp430_hcodes): Likewise..2004-08-13 Nick Clifton <nickc@redhat.com>PR/301* h8300.h (O_JSR): Do not allow VECIND addressing for non-SXprocessors.2004-08-30 Michal Ludvig <mludvig@suse.cz>* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.2004-07-22 H.J. Lu <hongjiu.lu@intel.com>* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.2004-07-21 Jan Beulich <jbeulich@novell.com>* i386.h: Adjust instruction descriptions to better match thespecification.2004-07-16 Richard Earnshaw <rearnsha@arm.com>* arm.h: Remove all old content. Replace with architecture definesfrom gas/config/tc-arm.c.2004-07-09 Andreas Schwab <schwab@suse.de>* m68k.h: Fix comment.2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>* crx.h: New file.2004-06-24 Alan Modra <amodra@bigpond.net.au>* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.2004-05-24 Peter Barada <peter@the-baradas.com>* m68k.h: Add 'size' to m68k_opcode.2004-05-05 Peter Barada <peter@the-baradas.com>* m68k.h: Switch from ColdFire chip name to core variant.2004-04-22 Peter Barada <peter@the-baradas.com>* m68k.h: Add mcfmac/mcfemac definitions. Update operanddescriptions for new EMAC cases.Remove ColdFire macmw/macml/msacmw/msacmw hacks and properlyhandle Motorola MAC syntax.Allow disassembly of ColdFire V4e object files.2004-03-16 Alan Modra <amodra@bigpond.net.au>* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.2004-03-12 Jakub Jelinek <jakub@redhat.com>* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.2004-03-12 Michal Ludvig <mludvig@suse.cz>* i386.h (i386_optab): Added xstore as an alias for xstorerng.2004-03-12 Michal Ludvig <mludvig@suse.cz>* i386.h (i386_optab): Added xstore/xcrypt insns.2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>* h8300.h (32bit ldc/stc): Add relaxing support.2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>* h8300.h (BITOP): Pass MEMRELAX flag.2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32except for the H8S.For older changes see ChangeLog-9103Local Variables:mode: change-logleft-margin: 8fill-column: 74version-control: neverEnd:
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