OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-ia64/] [tlsbin.dd] - Rev 82

Go to most recent revision | Compare with Previous | Blame | View Log

#source: tlsbinpic.s
#source: tlsbin.s
#as:
#ld: -shared
#objdump: -drj.text
#target: ia64-*-*

.*: +file format elf..-ia64-.*

Disassembly of section .text:

40+1000 <fn2>:
40+1000:        10 10 15 06 80 05[      ]+\[MIB\][      ]+alloc r34=ar.pfs,5,3,0
40+1006:        10 02 00 62 00 00[      ]+mov r33=b0
40+100c:        00 00 00 20[    ]+nop.b 0x0
40+1010:        0d 70 .0 0. 00 24[      ]+\[MFI\][      ]+addl r14=(24|32|40|48|56|64),r1
40+1016:        00 00 00 02 00 e0[      ]+nop.f 0x0
40+101c:        .1 0. 00 90[    ]+addl r15=(24|32|40|48|56|64),r1;;
40+1020:        19 18 01 1c 18 10[      ]+\[MMB\][      ]+ld8 r35=\[r14\]
40+1026:        40 02 3c 30 20 00[      ]+ld8 r36=\[r15\]
40+102c:        [0-9a-f         ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
40+1030:        0d 70 .0 0. 00 24[      ]+\[MFI\][      ]+addl r14=(24|32|40|48|56|64),r1
40+1036:        00 00 00 02 00 e0[      ]+nop.f 0x0
40+103c:        .1 0. 00 90[    ]+addl r15=(24|32|40|48|56|64),r1;;
40+1040:        19 18 01 1c 18 10[      ]+\[MMB\][      ]+ld8 r35=\[r14\]
40+1046:        40 02 3c 30 20 00[      ]+ld8 r36=\[r15\]
40+104c:        [0-9a-f         ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
40+1050:        0d 70 .0 0. 00 24[      ]+\[MFI\][      ]+addl r14=(24|32|40|48|56|64),r1
40+1056:        00 00 00 02 00 80[      ]+nop.f 0x0
40+105c:        14 02 00 90[    ]+mov r36=33;;
40+1060:        1d 18 01 1c 18 10[      ]+\[MFB\][      ]+ld8 r35=\[r14\]
40+1066:        00 00 00 02 00 00[      ]+nop.f 0x0
40+106c:        [0-9a-f         ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
40+1070:        0d 70 .0 0. 00 24[      ]+\[MFI\][      ]+addl r14=(24|32|40|48|56|64),r1
40+1076:        00 00 00 02 00 80[      ]+nop.f 0x0
40+107c:        04 00 00 84[    ]+mov r36=r0;;
40+1080:        1d 18 01 1c 18 10[      ]+\[MFB\][      ]+ld8 r35=\[r14\]
40+1086:        00 00 00 02 00 00[      ]+nop.f 0x0
40+108c:        [0-9a-f         ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
40+1090:        0b 10 00 10 00 21[      ]+\[MMI\][      ]+mov r2=r8;;
40+1096:        e0 00 0a 00 48 e0[      ]+addl r14=64,r2
40+109c:        61 14 00 90[    ]+addl r15=70,r2;;
40+10a0:        05 70 2c 11 00 21[      ]+\[MLX\][      ]+adds r14=75,r8
40+10a6:        00 00 00 00 00 e0[      ]+movl r15=0x4d;;
40+10ac:        d1 04 00 60 
40+10b0:        0a 78 3c 10 00 20[      ]+\[MMI\][      ]+add r15=r15,r8;;
40+10b6:        00 00 00 02 00 00[      ]+nop.m 0x0
40+10bc:        20 02 aa 00[    ]+mov.i ar.pfs=r34
40+10c0:        11 00 00 00 01 00[      ]+\[MIB\][      ]+nop.m 0x0
40+10c6:        00 08 05 80 03 80[      ]+mov b0=r33
40+10cc:        08 00 84 00[    ]+br.ret.sptk.many b0;;

40+10d0 <_start>:
40+10d0:        0b 70 .0 0. 00 24[      ]+\[MMI\][      ]+addl r14=(24|32|40|48|56|64),r1;;
40+10d6:        e0 00 38 30 20 00[      ]+ld8 r14=\[r14\]
40+10dc:        00 00 04 00[    ]+nop.i 0x0;;
40+10e0:        0b 70 38 1a 00 20[      ]+\[MMI\][      ]+add r14=r14,r13;;
40+10e6:        e0 .0 0. 00 48 00[      ]+addl r14=(24|32|40|48|56|64),r1
40+10ec:        00 00 04 00[    ]+nop.i 0x0;;
40+10f0:        0b 70 00 1c 18 10[      ]+\[MMI\][      ]+ld8 r14=\[r14\];;
40+10f6:        e0 70 34 00 40 00[      ]+add r14=r14,r13
40+10fc:        00 00 04 00[    ]+nop.i 0x0;;
40+1100:        0b 10 00 1a 00 21[      ]+\[MMI\][      ]+mov r2=r13;;
40+1106:        e0 80 08 00 48 e0[      ]+addl r14=16,r2
40+110c:        61 11 04 90[    ]+addl r15=150,r2;;
40+1110:        05 70 5c 1b 00 21[      ]+\[MLX\][      ]+adds r14=87,r13
40+1116:        00 00 00 00 00 e0[      ]+movl r15=0x95;;
40+111c:        51 01 04 60 
40+1120:        0a 78 3c 1a 00 20[      ]+\[MMI\][      ]+add r15=r15,r13;;
40+1126:        00 00 00 02 00 00[      ]+nop.m 0x0
40+112c:        00 00 04 00[    ]+nop.i 0x0
40+1130:        1d 00 00 00 01 00[      ]+\[MFB\][      ]+nop.m 0x0
40+1136:        00 00 00 02 00 80[      ]+nop.f 0x0
40+113c:        08 00 84 00[    ]+br.ret.sptk.many b0;;

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.