URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-ia64/] [tlspic.dd] - Rev 82
Go to most recent revision | Compare with Previous | Blame | View Log
#source: tlspic1.s
#source: tlspic2.s
#as:
#ld:
#objdump: -drj.text
#target: ia64-*-*
.*: +file format elf..-ia64-.*
Disassembly of section .text:
0+1000 <fn1>:
+1000: 10 10 15 06 80 05[ ]+\[MIB\] +alloc r34=ar.pfs,5,3,0
+1006: 10 02 00 62 00 00[ ]+mov r33=b0
+100c: 00 00 00 20[ ]+nop.b 0x0
+1010: 0d 70 60 02 00 24[ ]+\[MFI\] +addl r14=24,r1
+1016: 00 00 00 02 00 e0[ ]+nop.f 0x0
+101c: 01 0a 00 90[ ]+addl r15=32,r1;;
+1020: 19 18 01 1c 18 10[ ]+\[MMB\] +ld8 r35=\[r14\]
+1026: 40 02 3c 30 20 00[ ]+ld8 r36=\[r15\]
+102c: [0-9a-f ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+1030: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=48,r1
+1036: 00 00 00 02 00 e0[ ]+nop.f 0x0
+103c: 01 0c 00 90[ ]+addl r15=64,r1;;
+1040: 19 18 01 1c 18 10[ ]+\[MMB\] +ld8 r35=\[r14\]
+1046: 40 02 3c 30 20 00[ ]+ld8 r36=\[r15\]
+104c: [0-9a-f ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+1050: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=48,r1
+1056: 00 00 00 02 00 80[ ]+nop.f 0x0
+105c: 14 02 00 90[ ]+mov r36=33;;
+1060: 1d 18 01 1c 18 10[ ]+\[MFB\] +ld8 r35=\[r14\]
+1066: 00 00 00 02 00 00[ ]+nop.f 0x0
+106c: [0-9a-f ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+1070: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=48,r1
+1076: 00 00 00 02 00 80[ ]+nop.f 0x0
+107c: 04 00 00 84[ ]+mov r36=r0;;
+1080: 1d 18 01 1c 18 10[ ]+\[MFB\] +ld8 r35=\[r14\]
+1086: 00 00 00 02 00 00[ ]+nop.f 0x0
+108c: [0-9a-f ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+1090: 0b 10 00 10 00 21[ ]+\[MMI\] +mov r2=r8;;
+1096: e0 00 0a 00 48 e0[ ]+addl r14=64,r2
+109c: 21 16 00 90[ ]+addl r15=98,r2;;
+10a0: 05 70 4c 11 00 21[ ]+\[MLX\] +adds r14=83,r8
+10a6: 00 00 00 00 00 e0[ ]+movl r15=0x71;;
+10ac: 11 07 00 60
+10b0: 0b 78 3c 10 00 20[ ]+\[MMI\] +add r15=r15,r8;;
+10b6: e0 40 05 00 48 00[ ]+addl r14=40,r1
+10bc: 00 00 04 00[ ]+nop.i 0x0;;
+10c0: 0b 78 00 1c 18 10[ ]+\[MMI\] +ld8 r15=\[r14\];;
+10c6: e0 78 34 00 40 00[ ]+add r14=r15,r13
+10cc: 00 00 04 00[ ]+nop.i 0x0;;
+10d0: 0d 70 20 03 00 24[ ]+\[MFI\] +addl r14=72,r1
+10d6: 00 00 00 02 00 e0[ ]+nop.f 0x0
+10dc: 81 0b 00 90[ ]+addl r15=56,r1;;
+10e0: 09 70 00 1c 18 10[ ]+\[MMI\] +ld8 r14=\[r14\]
+10e6: f0 00 3c 30 20 00[ ]+ld8 r15=\[r15\]
+10ec: 00 00 04 00[ ]+nop.i 0x0;;
+10f0: 02 70 38 1a 00 20[ ]+\[MII\] +add r14=r14,r13
+10f6: f0 78 34 00 40 00[ ]+add r15=r15,r13;;
+10fc: 20 02 aa 00[ ]+mov.i ar.pfs=r34
+1100: 11 00 00 00 01 00[ ]+\[MIB\] +nop.m 0x0
+1106: 00 08 05 80 03 80[ ]+mov b0=r33
+110c: 08 00 84 00[ ]+br.ret.sptk.many b0;;
#pass
Go to most recent revision | Compare with Previous | Blame | View Log