OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-tic6x/] [shlib-1.dd] - Rev 300

Go to most recent revision | Compare with Previous | Blame | View Log


tmpdir/libtest\.so:     file format elf32-tic6x-le


Disassembly of section \.plt:

10000020 <sub0@plt-0x18>:
10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
10000028:[ \t]*00004000[ \t]*nop 3
1000002c:[ \t]*00080362[ \t]*b \.S2 b2
10000030:[ \t]*00008000[ \t]*nop 5
10000034:[ \t]*00000000[ \t]*nop 1

10000038 <sub0@plt>:
10000038:[ \t]*0100056e[ \t]*ldw \.D2T2 \*\+b14\(20\),b2
1000003c:[ \t]*0000002a[ \t]*mvk \.S2 0,b0
10000040:[ \t]*0000006a[ \t]*mvkh \.S2 0,b0
10000044:[ \t]*00002000[ \t]*nop 2
10000048:[ \t]*00080362[ \t]*b \.S2 b2
1000004c:[ \t]*00008000[ \t]*nop 5

10000050 <sub@plt>:
10000050:[ \t]*0100066e[ \t]*ldw \.D2T2 \*\+b14\(24\),b2
10000054:[ \t]*0000062a[ \t]*mvk \.S2 12,b0
10000058:[ \t]*0000006a[ \t]*mvkh \.S2 0,b0
1000005c:[ \t]*00002000[ \t]*nop 2
10000060:[ \t]*00080362[ \t]*b \.S2 b2
10000064:[ \t]*00008000[ \t]*nop 5
        \.\.\.

Disassembly of section \.text:

10000080 <sub1>:
10000080:[ \t]*000c0362[ \t]*b \.S2 b3
10000084:[ \t]*00008000[ \t]*nop 5

10000088 <sub0>:
10000088:[ \t]*07be09c2[ \t]*sub \.D2 b15,16,b15
1000008c:[ \t]*01bc62f6[ \t]*stw \.D2T2 b3,\*\+b15\(12\)
10000090:[ \t]*073c82f6[ \t]*stw \.D2T2 b14,\*\+b15\(16\)
10000094:[ \t]*0700026e[ \t]*ldw \.D2T2 \*\+b14\(8\),b14
10000098:[ \t]*0ffffa12[ \t]*b \.S2 10000050 <sub@plt>
1000009c:[ \t]*0ffff712[ \t]*b \.S2 10000038 <sub0@plt>
100000a0:[ \t]*0ffffc12[ \t]*b \.S2 10000080 <sub1>
100000a4:[ \t]*01bc62e6[ \t]*ldw \.D2T2 \*\+b15\(12\),b3
100000a8:[ \t]*073c82e6[ \t]*ldw \.D2T2 \*\+b15\(16\),b14
100000ac:[ \t]*07800852[ \t]*addk \.S2 16,b15
100000b0:[ \t]*00004000[ \t]*nop 3
100000b4:[ \t]*000c0362[ \t]*b \.S2 b3
100000b8:[ \t]*00008000[ \t]*nop 5
100000bc:[ \t]*00000000[ \t]*nop 1

100000c0 <sub>:
100000c0:[ \t]*07be09c2[ \t]*sub \.D2 b15,16,b15
100000c4:[ \t]*023c62f4[ \t]*stw \.D2T1 a4,\*\+b15\(12\)
100000c8:[ \t]*003c62e4[ \t]*ldw \.D2T1 \*\+b15\(12\),a0
100000cc:[ \t]*00006000[ \t]*nop 4
100000d0:[ \t]*00014940[ \t]*add \.D1 a0,10,a0
100000d4:[ \t]*020008f0[ \t]*or \.D1 0,a0,a4
100000d8:[ \t]*07be0942[ \t]*add \.D2 b15,16,b15
100000dc:[ \t]*000c0362[ \t]*b \.S2 b3
100000e0:[ \t]*0300096e[ \t]*ldw \.D2T2 \*\+b14\(36\),b6
100000e4:[ \t]*0380076e[ \t]*ldw \.D2T2 \*\+b14\(28\),b7
100000e8:[ \t]*0400086e[ \t]*ldw \.D2T2 \*\+b14\(32\),b8
100000ec:[ \t]*04800c6e[ \t]*ldw \.D2T2 \*\+b14\(48\),b9
        \.\.\.

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.