OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-tic6x/] [shlib-noindex.dd] - Rev 117

Compare with Previous | Blame | View Log


tmpdir/libtestn\.so:     file format elf32-tic6x-le


Disassembly of section \.plt:

10000020 <sub0@plt-0x18>:
10000020:       0100036e        ldw \.D2T2 \*\+b14\(12\),b2
10000024:       0080046e        ldw \.D2T2 \*\+b14\(16\),b1
10000028:       00004000        nop 3
1000002c:       00080362        b \.S2 b2
10000030:       00008000        nop 5
10000034:       00000000        nop 1

10000038 <sub0@plt>:
10000038:       0100056e        ldw \.D2T2 \*\+b14\(20\),b2
1000003c:       0000002a        mvk \.S2 0,b0
10000040:       0000006a        mvkh \.S2 0,b0
10000044:       00002000        nop 2
10000048:       00080362        b \.S2 b2
1000004c:       00008000        nop 5

10000050 <sub@plt>:
10000050:       0100066e        ldw \.D2T2 \*\+b14\(24\),b2
10000054:       0000062a        mvk \.S2 12,b0
10000058:       0000006a        mvkh \.S2 0,b0
1000005c:       00002000        nop 2
10000060:       00080362        b \.S2 b2
10000064:       00008000        nop 5
        \.\.\.

Disassembly of section \.text:

10000080 <sub1>:
10000080:       000c0362        b \.S2 b3
10000084:       00008000        nop 5

10000088 <sub0>:
10000088:       07be09c2        sub \.D2 b15,16,b15
1000008c:       01bc62f6        stw \.D2T2 b3,\*\+b15\(12\)
10000090:       073c82f6        stw \.D2T2 b14,\*\+b15\(16\)
10000094:       0700006e        ldw \.D2T2 \*\+b14\(0\),b14
10000098:       0ffffa12        b \.S2 10000050 <sub@plt>
1000009c:       0ffff712        b \.S2 10000038 <sub0@plt>
100000a0:       0ffffc12        b \.S2 10000080 <sub1>
100000a4:       01bc62e6        ldw \.D2T2 \*\+b15\(12\),b3
100000a8:       073c82e6        ldw \.D2T2 \*\+b15\(16\),b14
100000ac:       07800852        addk \.S2 16,b15
100000b0:       00004000        nop 3
100000b4:       000c0362        b \.S2 b3
100000b8:       00008000        nop 5
100000bc:       00000000        nop 1

100000c0 <sub>:
100000c0:       07be09c2        sub \.D2 b15,16,b15
100000c4:       023c62f4        stw \.D2T1 a4,\*\+b15\(12\)
100000c8:       003c62e4        ldw \.D2T1 \*\+b15\(12\),a0
100000cc:       00006000        nop 4
100000d0:       00014940        add \.D1 a0,10,a0
100000d4:       020008f0        or \.D1 0,a0,a4
100000d8:       07be0942        add \.D2 b15,16,b15
100000dc:       000c0362        b \.S2 b3
100000e0:       0300096e        ldw \.D2T2 \*\+b14\(36\),b6
100000e4:       0380076e        ldw \.D2T2 \*\+b14\(28\),b7
100000e8:       0400086e        ldw \.D2T2 \*\+b14\(32\),b8
100000ec:       04800c6e        ldw \.D2T2 \*\+b14\(48\),b9
        \.\.\.

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.