URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [i386-reg.tbl] - Rev 51
Go to most recent revision | Compare with Previous | Blame | View Log
// i386 register table.// Copyright 2007, 2008// Free Software Foundation, Inc.//// This file is part of the GNU opcodes library.//// This library is free software; you can redistribute it and/or modify// it under the terms of the GNU General Public License as published by// the Free Software Foundation; either version 3, or (at your option)// any later version.//// It is distributed in the hope that it will be useful, but WITHOUT// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public// License for more details.//// You should have received a copy of the GNU General Public License// along with GAS; see the file COPYING. If not, write to the Free// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA// 02110-1301, USA.// Make %st first as we test for it.st, FloatReg|FloatAcc, 0, 0, 11, 33// 8 bit regsal, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Invalcl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Invaldl, Reg8, 0, 2, Dw2Inval, Dw2Invalbl, Reg8, 0, 3, Dw2Inval, Dw2Invalah, Reg8, 0, 4, Dw2Inval, Dw2Invalch, Reg8, 0, 5, Dw2Inval, Dw2Invaldh, Reg8, 0, 6, Dw2Inval, Dw2Invalbh, Reg8, 0, 7, Dw2Inval, Dw2Invalaxl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Invalcxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Invaldxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Invalbxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Invalspl, Reg8, RegRex64, 4, Dw2Inval, Dw2Invalbpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Invalsil, Reg8, RegRex64, 6, Dw2Inval, Dw2Invaldil, Reg8, RegRex64, 7, Dw2Inval, Dw2Invalr8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Invalr9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Invalr10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Invalr11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Invalr12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Invalr13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Invalr14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Invalr15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval// 16 bit regsax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Invalcx, Reg16, 0, 1, Dw2Inval, Dw2Invaldx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Invalbx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Invalsp, Reg16, 0, 4, Dw2Inval, Dw2Invalbp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Invalsi, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Invaldi, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Invalr8w, Reg16, RegRex, 0, Dw2Inval, Dw2Invalr9w, Reg16, RegRex, 1, Dw2Inval, Dw2Invalr10w, Reg16, RegRex, 2, Dw2Inval, Dw2Invalr11w, Reg16, RegRex, 3, Dw2Inval, Dw2Invalr12w, Reg16, RegRex, 4, Dw2Inval, Dw2Invalr13w, Reg16, RegRex, 5, Dw2Inval, Dw2Invalr14w, Reg16, RegRex, 6, Dw2Inval, Dw2Invalr15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval// 32 bit regseax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Invalecx, Reg32|BaseIndex, 0, 1, 1, Dw2Invaledx, Reg32|BaseIndex, 0, 2, 2, Dw2Invalebx, Reg32|BaseIndex, 0, 3, 3, Dw2Invalesp, Reg32, 0, 4, 4, Dw2Invalebp, Reg32|BaseIndex, 0, 5, 5, Dw2Invalesi, Reg32|BaseIndex, 0, 6, 6, Dw2Invaledi, Reg32|BaseIndex, 0, 7, 7, Dw2Invalr8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Invalr9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Invalr10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Invalr11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Invalr12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Invalr13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Invalr14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Invalr15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Invalrax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3rsp, Reg64, 0, 4, Dw2Inval, 7rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15// Segment registers.es, SReg2, 0, 0, 40, 50cs, SReg2, 0, 1, 41, 51ss, SReg2, 0, 2, 42, 52ds, SReg2, 0, 3, 43, 53fs, SReg3, 0, 4, 44, 54gs, SReg3, 0, 5, 45, 55flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval// Control registers.cr0, Control, 0, 0, Dw2Inval, Dw2Invalcr1, Control, 0, 1, Dw2Inval, Dw2Invalcr2, Control, 0, 2, Dw2Inval, Dw2Invalcr3, Control, 0, 3, Dw2Inval, Dw2Invalcr4, Control, 0, 4, Dw2Inval, Dw2Invalcr5, Control, 0, 5, Dw2Inval, Dw2Invalcr6, Control, 0, 6, Dw2Inval, Dw2Invalcr7, Control, 0, 7, Dw2Inval, Dw2Invalcr8, Control, RegRex, 0, Dw2Inval, Dw2Invalcr9, Control, RegRex, 1, Dw2Inval, Dw2Invalcr10, Control, RegRex, 2, Dw2Inval, Dw2Invalcr11, Control, RegRex, 3, Dw2Inval, Dw2Invalcr12, Control, RegRex, 4, Dw2Inval, Dw2Invalcr13, Control, RegRex, 5, Dw2Inval, Dw2Invalcr14, Control, RegRex, 6, Dw2Inval, Dw2Invalcr15, Control, RegRex, 7, Dw2Inval, Dw2Inval// Debug registers.db0, Debug, 0, 0, Dw2Inval, Dw2Invaldb1, Debug, 0, 1, Dw2Inval, Dw2Invaldb2, Debug, 0, 2, Dw2Inval, Dw2Invaldb3, Debug, 0, 3, Dw2Inval, Dw2Invaldb4, Debug, 0, 4, Dw2Inval, Dw2Invaldb5, Debug, 0, 5, Dw2Inval, Dw2Invaldb6, Debug, 0, 6, Dw2Inval, Dw2Invaldb7, Debug, 0, 7, Dw2Inval, Dw2Invaldb8, Debug, RegRex, 0, Dw2Inval, Dw2Invaldb9, Debug, RegRex, 1, Dw2Inval, Dw2Invaldb10, Debug, RegRex, 2, Dw2Inval, Dw2Invaldb11, Debug, RegRex, 3, Dw2Inval, Dw2Invaldb12, Debug, RegRex, 4, Dw2Inval, Dw2Invaldb13, Debug, RegRex, 5, Dw2Inval, Dw2Invaldb14, Debug, RegRex, 6, Dw2Inval, Dw2Invaldb15, Debug, RegRex, 7, Dw2Inval, Dw2Invaldr0, Debug, 0, 0, Dw2Inval, Dw2Invaldr1, Debug, 0, 1, Dw2Inval, Dw2Invaldr2, Debug, 0, 2, Dw2Inval, Dw2Invaldr3, Debug, 0, 3, Dw2Inval, Dw2Invaldr4, Debug, 0, 4, Dw2Inval, Dw2Invaldr5, Debug, 0, 5, Dw2Inval, Dw2Invaldr6, Debug, 0, 6, Dw2Inval, Dw2Invaldr7, Debug, 0, 7, Dw2Inval, Dw2Invaldr8, Debug, RegRex, 0, Dw2Inval, Dw2Invaldr9, Debug, RegRex, 1, Dw2Inval, Dw2Invaldr10, Debug, RegRex, 2, Dw2Inval, Dw2Invaldr11, Debug, RegRex, 3, Dw2Inval, Dw2Invaldr12, Debug, RegRex, 4, Dw2Inval, Dw2Invaldr13, Debug, RegRex, 5, Dw2Inval, Dw2Invaldr14, Debug, RegRex, 6, Dw2Inval, Dw2Invaldr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval// Test registers.tr0, Test, 0, 0, Dw2Inval, Dw2Invaltr1, Test, 0, 1, Dw2Inval, Dw2Invaltr2, Test, 0, 2, Dw2Inval, Dw2Invaltr3, Test, 0, 3, Dw2Inval, Dw2Invaltr4, Test, 0, 4, Dw2Inval, Dw2Invaltr5, Test, 0, 5, Dw2Inval, Dw2Invaltr6, Test, 0, 6, Dw2Inval, Dw2Invaltr7, Test, 0, 7, Dw2Inval, Dw2Inval// MMX and simd registers.mm0, RegMMX, 0, 0, 29, 41mm1, RegMMX, 0, 1, 30, 42mm2, RegMMX, 0, 2, 31, 43mm3, RegMMX, 0, 3, 32, 44mm4, RegMMX, 0, 4, 33, 45mm5, RegMMX, 0, 5, 34, 46mm6, RegMMX, 0, 6, 35, 47mm7, RegMMX, 0, 7, 36, 48xmm0, RegXMM, 0, 0, 21, 17xmm1, RegXMM, 0, 1, 22, 18xmm2, RegXMM, 0, 2, 23, 19xmm3, RegXMM, 0, 3, 24, 20xmm4, RegXMM, 0, 4, 25, 21xmm5, RegXMM, 0, 5, 26, 22xmm6, RegXMM, 0, 6, 27, 23xmm7, RegXMM, 0, 7, 28, 24xmm8, RegXMM, RegRex, 0, Dw2Inval, 25xmm9, RegXMM, RegRex, 1, Dw2Inval, 26xmm10, RegXMM, RegRex, 2, Dw2Inval, 27xmm11, RegXMM, RegRex, 3, Dw2Inval, 28xmm12, RegXMM, RegRex, 4, Dw2Inval, 29xmm13, RegXMM, RegRex, 5, Dw2Inval, 30xmm14, RegXMM, RegRex, 6, Dw2Inval, 31xmm15, RegXMM, RegRex, 7, Dw2Inval, 32// AVX registers.ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Invalymm1, RegYMM, 0, 1, Dw2Inval, Dw2Invalymm2, RegYMM, 0, 2, Dw2Inval, Dw2Invalymm3, RegYMM, 0, 3, Dw2Inval, Dw2Invalymm4, RegYMM, 0, 4, Dw2Inval, Dw2Invalymm5, RegYMM, 0, 5, Dw2Inval, Dw2Invalymm6, RegYMM, 0, 6, Dw2Inval, Dw2Invalymm7, RegYMM, 0, 7, Dw2Inval, Dw2Invalymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Invalymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Invalymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Invalymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Invalymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Invalymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Invalymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Invalymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval// No type will make these registers rejected for all purposes except// for addressing. This saves creating one extra type for RIP/EIP.rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval// No type will make these registers rejected for all purposes except// for addressing.eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Invalriz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval// fp regs.st(0), FloatReg|FloatAcc, 0, 0, 11, 33st(1), FloatReg, 0, 1, 12, 34st(2), FloatReg, 0, 2, 13, 35st(3), FloatReg, 0, 3, 14, 36st(4), FloatReg, 0, 4, 15, 37st(5), FloatReg, 0, 5, 16, 38st(6), FloatReg, 0, 6, 17, 39st(7), FloatReg, 0, 7, 18, 40// Pseudo-register names only used in .cfi_* directiveseflags, 0, 0, 0, 9, 49rflags, 0, 0, 0, Dw2Inval, 49fs.base, 0, 0, 0, Dw2Inval, 58gs.base, 0, 0, 0, Dw2Inval, 59tr, 0, 0, 0, 48, 62ldtr, 0, 0, 0, 49, 63// st0...7 for backward compatibilityst0, 0, 0, 0, 11, 33st1, 0, 0, 1, 12, 34st2, 0, 0, 2, 13, 35st3, 0, 0, 3, 14, 36st4, 0, 0, 4, 15, 37st5, 0, 0, 5, 16, 38st6, 0, 0, 6, 17, 39st7, 0, 0, 7, 18, 40fcw, 0, 0, 0, 37, 65fsw, 0, 0, 0, 38, 66mxcsr, 0, 0, 0, 39, 64
Go to most recent revision | Compare with Previous | Blame | View Log