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////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	xioddrserdes.v
//
// Project:	A wishbone controlled DDR3 SDRAM memory controller.
//
// Purpose:	
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module	xioddrserdes(i_clk_fast, i_clk_fast_inv, i_clk_slow, i_reset,
		i_oe, i_data, o_data, io_pin);
	input			i_clk_fast, i_clk_fast_inv, i_clk_slow, i_reset;
	input			i_oe;
	input		[7:0]	i_data;
	output	wire	[7:0]	o_data;
	inout			io_pin;
 
	wire		feedback;
	wire		oe_for_fabric__unconnected;
	wire	[1:0]	local_shiftout__unconnected;
	wire		local_tbyte_out__unconnected;
	wire		send_to_iob;
	wire		oe_for_iob;
	wire	[1:0]	iserdes_shiftout__unconnected;
 
	OSERDESE2	#(
			.DATA_RATE_OQ("DDR"),
			.DATA_RATE_TQ("BUF"),
			.DATA_WIDTH(8), // 8 data wires sent per clkdiv
			.INIT_OQ(1'b1),
			.SERDES_MODE("MASTER"),
			// 
			.TRISTATE_WIDTH(1),
			.INIT_TQ(1'b1),
			.TBYTE_CTL("FALSE"),
			.TBYTE_SRC("FALSE")
		) oserdes_i(
			.CLK(i_clk_fast),
			.CLKDIV(i_clk_slow),
			.OCE(1'b1),
			.OFB(feedback),
			.OQ(send_to_iob),
			.RST(i_reset),
			//
			.TCE(1'b1),
			.TQ(oe_for_iob),
			.TFB(oe_for_fabric__unconnected),
			.T1(~i_oe), .T2(~i_oe), .T3(~i_oe), .T4(~i_oe),
			//
			.SHIFTOUT1(local_shiftout__unconnected[0]),
			.SHIFTOUT2(local_shiftout__unconnected[1]),
			.SHIFTIN1(1'b0),
			.SHIFTIN2(1'b0),
			.TBYTEIN(1'b0),
			.TBYTEOUT(local_tbyte_out__unconnected),
			//
			// And now for the actual data we wish to send
			//
			.D1(i_data[0]), .D2(i_data[1]),
			.D3(i_data[2]), .D4(i_data[3]),
			.D5(i_data[4]), .D6(i_data[5]),
			.D7(i_data[6]), .D8(i_data[7])
		);
 
	IOBUF	iobuf_i(
			.T(oe_for_iob),
			.I(send_to_iob),
			.IO(io_pin),
			.O(input_from_iobuf));
 
	ISERDESE2	#(
			.DATA_RATE("DDR"),
			.DATA_WIDTH(8), // 8 data wires sent per clkdiv
			.INTERFACE_TYPE("OVERSAMPLE"),
			.IOBDELAY("NONE"),
			.NUM_CE(1),
			.OFB_USED("FALSE"),
			.SERDES_MODE("MASTER")
		) iserdes_i(
			.BITSLIP(1'b0),
			.CE1(1'b1),
			.CE2(1'b1),
			.CLK(i_clk_fast),
			.CLKB(i_clk_fast_inv),
			.CLKDIV(i_clk_slow),
			.CLKDIVP(1'b0),	// Only used in MEMORY_DDR3 mode?
			.D(input_from_iobuf),
			.DDLY(1'b0),
			.DYNCLKDIVSEL(1'b0),
			.DYNCLKSEL(1'b0),
			.O(iserdes_unconnected_output),
			.OCLK(i_clk_fast),
			.OCLKB(i_clk_fast_inv),
			.OFB(feedback),
			.Q1(o_data[0]), .Q2(o_data[1]),
			.Q3(o_data[2]), .Q4(o_data[3]),
			.Q5(o_data[4]), .Q6(o_data[5]),
			.Q7(o_data[6]), .Q8(o_data[7]),
			.RST(i_reset),
			.SHIFTIN1(1'b0), .SHIFTIN2(1'b0),
			.SHIFTOUT1(iserdes_shiftout__unconnected[0]),
			.SHIFTOUT2(iserdes_shiftout__unconnected[1])
		);
 
endmodule