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////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	sdramscope.cpp
//
// Project:	XuLA2-LX25 SoC based upon the ZipCPU
//
// Purpose:	This file decodes the debug bits produced by the wbicapetwo.v
//		Verilog module, and stored in a Wishbone Scope.  It is useful
//	for determining if the scope works at all or not.  (The scope does work
//	... now ... and it turned out the most recent bugs were found in the
//	bus interconnect rather than the wbicapetwo module itself.  Still ...
//	the wbicapetwo module was updated with an adjustable clock, so
//	things always get better ... right?)
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <strings.h>
#include <ctype.h>
#include <string.h>
#include <signal.h>
#include <assert.h>
 
#include "port.h"
#include "regdefs.h"
#include "scopecls.h"
 
#define	WBSCOPE		R_CFGSCOPE
#define	WBSCOPEDATA	R_CFGSCOPED
 
FPGA	*m_fpga;
void	closeup(int v) {
	m_fpga->kill();
	exit(0);
}
 
class	CFGSCOPE : public SCOPE {
public:
	CFGSCOPE(FPGA *fpga, unsigned addr, bool vecread)
		: SCOPE(fpga, addr, false, false) {};
	~CFGSCOPE(void) {}
	virtual	void	decode(DEVBUS::BUSW val) const {
		int	clk, ckstb, ckstl,
			wbstb, wbstl, wback,
			csn, rdwrn, state,
			cfgin, cfgout;
 
		clk      = (val>>30)&1;
		ckstb    = (val>>29)&1;
		ckstl    = (val>>28)&1;
		wbstb    = (val>>27)&1;
		wback    = (val>>26)&1;
		csn      = (val>>25)&1;
		rdwrn    = (val>>24)&1;
		wbstl    = (val>>23)&1;
		state    = (val>>18)&0x1f;
		cfgin    = (val>> 8)&0x0ff;
		cfgout   = (val    )&0x0ff;
 
		printf("%s %s/%s  [%d%d%d] %2x [%02x - %02x]",
			(wbstb)?"STB":"   ",
			(wbstl)?"STL":"   ",
			(wback)?"ACK":"   ",
			clk, ckstb, ckstl,
			state, cfgin, cfgout);
	}
};
 
int main(int argc, char **argv) {
	FPGAOPEN(m_fpga);
 
	signal(SIGSTOP, closeup);
	signal(SIGHUP, closeup);
 
	CFGSCOPE *scope = new CFGSCOPE(m_fpga, WBSCOPE, false);
	if (!scope->ready()) {
		printf("Scope is not yet ready:\n");
		scope->decode_control();
	} else
		scope->read();
	delete	m_fpga;
}